Presentation 2018-12-06
Multi-FPGA implementation of deep learning applications
Kazusa Musha, Akram Ben Ahmed, Kudoh Tomohiro, Hideharu Amano,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) FiC (Flow-in-Cloud) -SW is an FPGA-based switch board for deep learning applications. In this paper, we implemented a deep learning application on a multi FiC-SW system, and evaluated execution time and power efficiency. As a result, we achieved the power performance 6.74 GOPS/W as well as the latest FPGA research, and high execution performance 482 GOPS exceeding single FPGA by multi FPGA.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / Multi-FPGA / Deep Learning
Paper # RECONF2018-40
Date of Issue 2018-11-28 (RECONF)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2018/12/5(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Satellite Campus Hiroshima
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2018 -New Field of VLSI Design-
Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大)
Vice Chair Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII)
Secretary Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research)
Assistant / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Multi-FPGA implementation of deep learning applications
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Multi-FPGA
Keyword(3) Deep Learning
1st Author's Name Kazusa Musha
1st Author's Affiliation Keio University(Keio Univ.)
2nd Author's Name Akram Ben Ahmed
2nd Author's Affiliation Keio University(Keio Univ.)
3rd Author's Name Kudoh Tomohiro
3rd Author's Affiliation University of Tokyo(Univ. of Tokyo)
4th Author's Name Hideharu Amano
4th Author's Affiliation Keio University(Keio Univ.)
Date 2018-12-06
Paper # RECONF2018-40
Volume (vol) vol.118
Number (no) RECONF-340
Page pp.pp.33-38(RECONF),
#Pages 6
Date of Issue 2018-11-28 (RECONF)