Presentation 2018-12-06
An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / hardware offload / DNS query / domain name
Paper # VLD2018-55,DC2018-41
Date of Issue 2018-11-28 (VLD, DC)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2018/12/5(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Satellite Campus Hiroshima
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2018 -New Field of VLSI Design-
Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大)
Vice Chair Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII)
Secretary Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research)
Assistant / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) hardware offload
Keyword(3) DNS query
Keyword(4) domain name
1st Author's Name Shoko Ohteru
1st Author's Affiliation NTT Corporation(NTT)
2nd Author's Name Saki Hatta
2nd Author's Affiliation NTT Corporation(NTT)
3rd Author's Name Tomoaki Kawamura
3rd Author's Affiliation NTT Corporation(NTT)
4th Author's Name Koji Yamazaki
4th Author's Affiliation NTT Advanced Technology Corporation(NTT-AT)
5th Author's Name Takahiro Hatano
5th Author's Affiliation NTT Corporation(NTT)
6th Author's Name Akihiko Miyazaki
6th Author's Affiliation NTT Corporation(NTT)
7th Author's Name Koyo Nitta
7th Author's Affiliation NTT Corporation(NTT)
Date 2018-12-06
Paper # VLD2018-55,DC2018-41
Volume (vol) vol.118
Number (no) VLD-334,DC-335
Page pp.pp.113-118(VLD), pp.113-118(DC),
#Pages 6
Date of Issue 2018-11-28 (VLD, DC)