| Presentation | 2018-12-07 An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A compact multiplier circuit is designed by time-encoded stochastic computing technology. The operands of multiplication are represented by the cycle duty of pulse signals. Using the Neuron-MOS technology, an efficiently tunable pulse-generator is proposed without digital pulse-width-modulation (PWM). The multiplication of two time-encoded stochastic numbers is obtained through a simple logic gate. The proof-of-concept multiplier is designed in a 0.18um CMOS technology. The total amount of MOS transistors is reduced to 3% of the traditional time-encoded stochastic calculator. From the circuit simulation results, the calculation accuracy of 85% is achieved; and the energy for one single operation is slightly reduced from the existing works with 5 x speed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Approximate Computing / Time-encoded Stochastic / Neuron-MOS |
| Paper # | CPSY2018-41 |
| Date of Issue | 2018-11-28 (CPSY) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2018/12/5(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大) |
| Vice Chair | Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII) |
| Secretary | Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit |
| Sub Title (in English) | |
| Keyword(1) | Approximate Computing |
| Keyword(2) | Time-encoded Stochastic |
| Keyword(3) | Neuron-MOS |
| 1st Author's Name | Tati Erlina |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 2nd Author's Name | Renyuan Zhang |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Yasuhiko Nakashima |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2018-12-07 |
| Paper # | CPSY2018-41 |
| Volume (vol) | vol.118 |
| Number (no) | CPSY-339 |
| Page | pp.pp.47-52(CPSY), |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (CPSY) |