| Presentation | 2018-12-06 Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | 3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs may cause small delay faults because of defects in TSVs such as voids and pinholes during the manufacturing process. We have been proposed a DFT(Design-For-Testability) method for TSVs using a boundary scan circuit with embedded TDC(TDCBS). The TDCBS has a circuit component called delay line that has two roles. One is to observe a delay in TSVs and the other is to apply a transition signal to TSV. In this paper, we present a design to separate the delay lines into two parts for delay observation and for transition signal application in order to reduce test application time on TDCBS. The proposed design can reduce test application time since the length of the scan chain is shortened by separating the delay lines. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | small delay fault / TSV / TDC / boundary scan / Design-For-Testability |
| Paper # | VLD2018-56,DC2018-42 |
| Date of Issue | 2018-11-28 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2018/12/5(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大) |
| Vice Chair | Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII) |
| Secretary | Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC |
| Sub Title (in English) | |
| Keyword(1) | small delay fault |
| Keyword(2) | TSV |
| Keyword(3) | TDC |
| Keyword(4) | boundary scan |
| Keyword(5) | Design-For-Testability |
| 1st Author's Name | Satoshi Hirai |
| 1st Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2018-12-06 |
| Paper # | VLD2018-56,DC2018-42 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-334,DC-335 |
| Page | pp.pp.119-124(VLD), pp.119-124(DC), |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (VLD, DC) |