| Presentation | 2018-11-22 [Poster Presentation] Signal Integrity Analysis for High-speed Memory Test Interface using Data Capture PCB Hyesoo Kim, Kyungjun Cho, Seongguk Kim, Joungho Kim, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, in high-speed graphic memory test interface, the trade-off relationship for electrical characteristic of the branch signal due to the branch structure and its degradation characteristics are analyzed in terms of signal integrity. A capture PCB is required in order to capture bit patterns for further failure analysis when GPU transmits signals to the high-speed graphic memory. The PCB is placed between prototype mother board and the memory. In the capture PCB, since signals are split into two, signal integrity is more degraded than before. Thus, this paper focuses on the reflection-analysis at the junction and discusses the trade-off among characteristics of received signal at the memory and captured signal depending on capture PCB design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Signal integrity analysis / PCB design / memory test |
| Paper # | EMCJ2018-80 |
| Date of Issue | 2018-11-15 (EMCJ) |
| Conference Information | |
| Committee | EMCJ / IEE-EMC / IEE-MAG |
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| Conference Date | 2018/11/22(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | KAIST |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | EMC Joint Workshop 2018, Daejon |
| Chair | Osami Wada(Kyoto Univ.) / Ken-ichi Yamazaki(Central Research Institute of Electric Power Industory) / Masahiro Yamaguchi(Tohoku Univ.) |
| Vice Chair | Kensei Oh(Nagoya Inst. of Tech.) |
| Secretary | Kensei Oh(Tokyo Inst. of Tech.) / (Mitsubishi Electric) / (Tohoku Gakuin Univ.) |
| Assistant | Shinobu Nagasawa(Mitsubishi Electric) / Shinichiro Yamamoto(Univ. of Hyogo) / Takanori Unou(Denso) / Takaaki Ibuchi(Osaka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Electromagnetic Compatibility / Technical Meeting on Electromagnetic Compatibility / Technical Meeting on Magnetics |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Signal Integrity Analysis for High-speed Memory Test Interface using Data Capture PCB |
| Sub Title (in English) | |
| Keyword(1) | Signal integrity analysis |
| Keyword(2) | PCB design |
| Keyword(3) | memory test |
| 1st Author's Name | Hyesoo Kim |
| 1st Author's Affiliation | Korea Advanced Institute of Science and Technology(KAIST) |
| 2nd Author's Name | Kyungjun Cho |
| 2nd Author's Affiliation | Korea Advanced Institute of Science and Technology(KAIST) |
| 3rd Author's Name | Seongguk Kim |
| 3rd Author's Affiliation | Korea Advanced Institute of Science and Technology(KAIST) |
| 4th Author's Name | Joungho Kim |
| 4th Author's Affiliation | Korea Advanced Institute of Science and Technology(KAIST) |
| Date | 2018-11-22 |
| Paper # | EMCJ2018-80 |
| Volume (vol) | vol.118 |
| Number (no) | EMCJ-317 |
| Page | pp.pp.63-63(EMCJ), |
| #Pages | 1 |
| Date of Issue | 2018-11-15 (EMCJ) |