講演名 2018-11-22
[Invited Talk] Security Simulation of Cryptographic Module in Side-Channel Attack
五百旗頭 健吾(岡山大), 豊田 啓孝(岡山大),
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抄録(和)
抄録(英) Side-channel attacks (SCAs) are one of the biggest threats to cryptography and one of important issues in IoT modules, closely related to the EMC field. If IoT modules are vulnerable to SCAs, cryptographic algorithms implemented in the module are no longer secure even when the algorithms are ensured mathematically secure. In an SCA, adversaries exploit unintentional noises of an integrated circuit (IC) on which the target cryptographic algorithm is implemented, such as electromagnetic emanation, voltage bounce in the power distribution network for the IC, and common-mode current and/or radiation. Those noises are caused by the dynamic switching current of the CMOS digital circuit that processes the target cryptographic operation and the intensity of the noise depends on processed data. SCAs can be realized if the data dependency of noise is detectable. For simulating security against SCAs on an Advanced Encryption Standard (AES) circuit, an equivalent circuit model of cryptographic IC was developed to estimate the data dependency in the power voltage bounce. The equivalent circuit model was confirmed that it produced a precise waveform simulation of power voltage bounce depending of data. As analyzing the data dependency of the simulated waveform, security of the AES circuit against SCA was also estimated in excellent accuracy. These results proved that the current source, a component of the equivalent circuit model, expresses the strength of side-channel information leakage of a cryptographic circuit. In our previous work, the equivalent circuit was modeled from measurements with a prototype of cryptographic module. In addition, we are studying for establishing a method to extract the current source from simulation based on a design information of cryptographic circuits. A preliminary result has been obtained suggesting that the current source can be extracted accurately from a power consumption simulation based on design information by using an EDA tool from IC venders.
キーワード(和)
キーワード(英) Side-channel attackEquivalent circuit modelAdvanced Encryption Standard (AES)Correlation power analysis
資料番号 EMCJ2018-61
発行日 2018-11-15 (EMCJ)

研究会情報
研究会 EMCJ / IEE-EMC / IEE-MAG
開催期間 2018/11/22(から2日開催)
開催地(和) KAIST(韓国大田市)
開催地(英) KAIST
テーマ(和) EMC Joint Workshop 2018, Daejon
テーマ(英) EMC Joint Workshop 2018, Daejon
委員長氏名(和) 和田 修己(京大) / 山崎 健一(電中研) / 山口 正洋(東北大)
委員長氏名(英) Osami Wada(Kyoto Univ.) / Ken-ichi Yamazaki(Central Research Institute of Electric Power Industory) / Masahiro Yamaguchi(Tohoku Univ.)
副委員長氏名(和) 王 建青(名工大)
副委員長氏名(英) Kensei Oh(Nagoya Inst. of Tech.)
幹事氏名(和) 青柳 貴洋(東工大) / 白木 康博(三菱電機) / 石上 忍(東北学院大) / 池畑 政輝(鉄道総研) / 小原 学(明治大) / 山田 啓壽(東芝)
幹事氏名(英) Takahiro Aoyagi(Tokyo Inst. of Tech.) / Yasuhiro Shiraki(Mitsubishi Electric) / Shinobu Ishigami(Tohoku Gakuin Univ.) / Masateru Ikehata(RTRI) / Gaku Obara(Meji Univ.) / Keiju Yamada(Toshiba Co.)
幹事補佐氏名(和) 長澤 忍(三菱電機) / 山本 真一郎(兵庫県立大) / 鵜生 高徳(デンソー) / 井渕 貴章(大阪大)
幹事補佐氏名(英) Shinobu Nagasawa(Mitsubishi Electric) / Shinichiro Yamamoto(Univ. of Hyogo) / Takanori Unou(Denso) / Takaaki Ibuchi(Osaka Univ.)

講演論文情報詳細
申込み研究会 Technical Committee on Electromagnetic Compatibility / Technical Meeting on Electromagnetic Compatibility / Technical Meeting on Magnetics
本文の言語 ENG
タイトル(和)
サブタイトル(和)
タイトル(英) [Invited Talk] Security Simulation of Cryptographic Module in Side-Channel Attack
サブタイトル(和)
キーワード(1)(和/英) / Side-channel attackEquivalent circuit modelAdvanced Encryption Standard (AES)Correlation power analysis
第 1 著者 氏名(和/英) 五百旗頭 健吾 / Kengo Iokibe
第 1 著者 所属(和/英) 岡山大学(略称:岡山大)
Okayama University(略称:Okayama Univ.)
第 2 著者 氏名(和/英) 豊田 啓孝 / Yoshitaka Toyota
第 2 著者 所属(和/英) 岡山大学(略称:岡山大)
Okayama University(略称:Okayama Univ.)
発表年月日 2018-11-22
資料番号 EMCJ2018-61
巻番号(vol) vol.118
号番号(no) EMCJ-317
ページ範囲 pp.19-19(EMCJ),
ページ数 1
発行日 2018-11-15 (EMCJ)