Presentation 2018-11-22
[Invited Talk] Security Simulation of Cryptographic Module in Side-Channel Attack
Kengo Iokibe, Yoshitaka Toyota,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Side-channel attacks (SCAs) are one of the biggest threats to cryptography and one of important issues in IoT modules, closely related to the EMC field. If IoT modules are vulnerable to SCAs, cryptographic algorithms implemented in the module are no longer secure even when the algorithms are ensured mathematically secure. In an SCA, adversaries exploit unintentional noises of an integrated circuit (IC) on which the target cryptographic algorithm is implemented, such as electromagnetic emanation, voltage bounce in the power distribution network for the IC, and common-mode current and/or radiation. Those noises are caused by the dynamic switching current of the CMOS digital circuit that processes the target cryptographic operation and the intensity of the noise depends on processed data. SCAs can be realized if the data dependency of noise is detectable. For simulating security against SCAs on an Advanced Encryption Standard (AES) circuit, an equivalent circuit model of cryptographic IC was developed to estimate the data dependency in the power voltage bounce. The equivalent circuit model was confirmed that it produced a precise waveform simulation of power voltage bounce depending of data. As analyzing the data dependency of the simulated waveform, security of the AES circuit against SCA was also estimated in excellent accuracy. These results proved that the current source, a component of the equivalent circuit model, expresses the strength of side-channel information leakage of a cryptographic circuit. In our previous work, the equivalent circuit was modeled from measurements with a prototype of cryptographic module. In addition, we are studying for establishing a method to extract the current source from simulation based on a design information of cryptographic circuits. A preliminary result has been obtained suggesting that the current source can be extracted accurately from a power consumption simulation based on design information by using an EDA tool from IC venders.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Side-channel attackEquivalent circuit modelAdvanced Encryption Standard (AES)Correlation power analysis
Paper # EMCJ2018-61
Date of Issue 2018-11-15 (EMCJ)

Conference Information
Committee EMCJ / IEE-EMC / IEE-MAG
Conference Date 2018/11/22(2days)
Place (in Japanese) (See Japanese page)
Place (in English) KAIST
Topics (in Japanese) (See Japanese page)
Topics (in English) EMC Joint Workshop 2018, Daejon
Chair Osami Wada(Kyoto Univ.) / Ken-ichi Yamazaki(Central Research Institute of Electric Power Industory) / Masahiro Yamaguchi(Tohoku Univ.)
Vice Chair Kensei Oh(Nagoya Inst. of Tech.)
Secretary Kensei Oh(Tokyo Inst. of Tech.) / (Mitsubishi Electric) / (Tohoku Gakuin Univ.)
Assistant Shinobu Nagasawa(Mitsubishi Electric) / Shinichiro Yamamoto(Univ. of Hyogo) / Takanori Unou(Denso) / Takaaki Ibuchi(Osaka Univ.)

Paper Information
Registration To Technical Committee on Electromagnetic Compatibility / Technical Meeting on Electromagnetic Compatibility / Technical Meeting on Magnetics
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Invited Talk] Security Simulation of Cryptographic Module in Side-Channel Attack
Sub Title (in English)
Keyword(1) Side-channel attackEquivalent circuit modelAdvanced Encryption Standard (AES)Correlation power analysis
1st Author's Name Kengo Iokibe
1st Author's Affiliation Okayama University(Okayama Univ.)
2nd Author's Name Yoshitaka Toyota
2nd Author's Affiliation Okayama University(Okayama Univ.)
Date 2018-11-22
Paper # EMCJ2018-61
Volume (vol) vol.118
Number (no) EMCJ-317
Page pp.pp.19-19(EMCJ),
#Pages 1
Date of Issue 2018-11-15 (EMCJ)