Presentation | 2018-12-06 Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In CAD for MPLD which is a type of fine grain reconfigurable PLD, the SA method is used as a place-ment method for logic elements. However, since the wiring structure of the MPLD is complicated, it is difficult to implement the cost function for the SA method as a simple mathematical model. Therefore, we considered implementing the cost function for the SA method with a neural network. In this paper, in order to ascertain whether a neural network that predicts the ease of wiring can be trained, we trained theneural network using the values from the conventional MPLD’s SA costfunction as pseudo learning data. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | MPLD / Placement and Route / SA(Simulated Annealing) / Neural Network |
Paper # | VLD2018-48,DC2018-34 |
Date of Issue | 2018-11-28 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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Conference Date | 2018/12/5(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Satellite Campus Hiroshima |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大) |
Vice Chair | Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII) |
Secretary | Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research) |
Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD |
Sub Title (in English) | |
Keyword(1) | MPLD |
Keyword(2) | Placement and Route |
Keyword(3) | SA(Simulated Annealing) |
Keyword(4) | Neural Network |
1st Author's Name | Hidehito Fujiishi |
1st Author's Affiliation | Hiroshima city University(Hiroshima city Univ.) |
2nd Author's Name | Tokio Kamada |
2nd Author's Affiliation | Hiroshima city University(Hiroshima city Univ.) |
3rd Author's Name | Tetsuo Hironaka |
3rd Author's Affiliation | Hiroshima city University(Hiroshima city Univ.) |
4th Author's Name | Kazuya Tanigawa |
4th Author's Affiliation | Hiroshima city University(Hiroshima city Univ.) |
5th Author's Name | Atsushi Kubota |
5th Author's Affiliation | Hiroshima city University(Hiroshima city Univ.) |
Date | 2018-12-06 |
Paper # | VLD2018-48,DC2018-34 |
Volume (vol) | vol.118 |
Number (no) | VLD-334,DC-335 |
Page | pp.pp.71-76(VLD), pp.71-76(DC), |
#Pages | 6 |
Date of Issue | 2018-11-28 (VLD, DC) |