| Presentation | 2018-10-18 On the Power-Aware MBU-Tolerant High-Level Synthesis Keisuke Inoue, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | CAS2018-37,NLP2018-72 |
| Date of Issue | 2018-10-11 (CAS, NLP) |
| Conference Information | |
| Committee | CAS / NLP |
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| Conference Date | 2018/10/18(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tohoku Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Mathematical modeling, numerical simulation etc. |
| Chair | Hideaki Okazaki(Shonan Inst. of Tech.) / Norikazu Takahashi(Okayama Univ.) |
| Vice Chair | Taizo Yamawaki(Hitachi) / Hiroaki Kurokawa(Tokyo Univ. of Tech.) |
| Secretary | Taizo Yamawaki(Shonan Inst. of Tech.) / Hiroaki Kurokawa(Hitachi) |
| Assistant | Motoi Yamaguchi(Renesas Electronics) / Masayuki Kimura(Kyoto Univ.) / Yutaka Shimada(Saitama Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Circuits and Systems / Technical Committee on Nonlinear Problems |
|---|---|
| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the Power-Aware MBU-Tolerant High-Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | |
| 1st Author's Name | Keisuke Inoue |
| 1st Author's Affiliation | International College of Technology, Kanazawa(ICT) |
| Date | 2018-10-18 |
| Paper # | CAS2018-37,NLP2018-72 |
| Volume (vol) | vol.118 |
| Number (no) | CAS-242,NLP-243 |
| Page | pp.pp.1-6(CAS), pp.1-6(NLP), |
| #Pages | 6 |
| Date of Issue | 2018-10-11 (CAS, NLP) |