| Presentation | 2018-10-29 An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with energy efficiency. As a solution to the problem there is a growing expectation of adopting advanced cryptography with rich functionalities such as searchable encryption which enables direct data retrieval over encrypted database without decrypting the database, and so on. Most of advanced cryptography use a pairing calculation as a component. It is required that we speed up a pairing calculation for the spread of advanced cryptography. In this paper, we describe how the record latency 91.2 ?s on FPGA board KCU105 for calculation of Optimal Ate pairing over BN curve on 254 bit prime field was achieved. The pairing calculator uses pipeline modular multipliers with improved scheduling for compressed squaring, reduced number of clock cycles on Miller Loop and Final Addition, and higher maximum operating frequency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware Security / Pairing Encryption / FPGA Implementation / Pipeline Implementation / Compressed Squaring |
| Paper # | HWS2018-50,ICD2018-42 |
| Date of Issue | 2018-10-22 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
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| Conference Date | 2018/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kobe Univ. Umeda Intelligent Laboratory |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | HardwareSecurity, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Hideto Hidaka(Renesas) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Makoto Nagata(Kobe Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Makoto Nagata(Panasonic) |
| Assistant | / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier |
| Sub Title (in English) | |
| Keyword(1) | Hardware Security |
| Keyword(2) | Pairing Encryption |
| Keyword(3) | FPGA Implementation |
| Keyword(4) | Pipeline Implementation |
| Keyword(5) | Compressed Squaring |
| 1st Author's Name | Yota Okuaki |
| 1st Author's Affiliation | Yokohama National University(YNU) |
| 2nd Author's Name | Junichi Sakamoto |
| 2nd Author's Affiliation | Yokohama National University(YNU) |
| 3rd Author's Name | Naoki Yoshida |
| 3rd Author's Affiliation | Yokohama National University(YNU) |
| 4th Author's Name | Daisuke Fujimoto |
| 4th Author's Affiliation | Yokohama National University(YNU) |
| 5th Author's Name | Tsutomu Matsumoto |
| 5th Author's Affiliation | Yokohama National University(YNU) |
| Date | 2018-10-29 |
| Paper # | HWS2018-50,ICD2018-42 |
| Volume (vol) | vol.118 |
| Number (no) | HWS-272,ICD-273 |
| Page | pp.pp.19-24(HWS), pp.19-24(ICD), |
| #Pages | 6 |
| Date of Issue | 2018-10-22 (HWS, ICD) |