| Presentation | 2018-10-30 [Poster Presentation] Transmitting Timing Calculation Unit with CPU on FPGA for QZSS Short Message SS-CDMA Communication Hiroshi Oguma, Rei Kawai, Takeshi Asai, Mizuki Motoyoshi, Mizuki Motoyoshi, Suguru Kameda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed synchronized Spread-Spectrum Code-Division Multiple-Acc ess (SS-CDMA) communication for location and short message communication system using Quasi-Zenith Satellite System (QZSS) as a safety confirmat ion system at the time of grade disaster. In the previous research, we h ave constructed a transmission timing control system for realizing synch ronous Spread-Spectrum Code-Division Multiple-Access (SS-CDMA) communica tion used in this communication system. Although the system was construc ted using the Micro Control Unit (MCU) and Field Programmable Gate Array (FPGA), it is necessary to consider SoC implementation of the system fo r improving the operating frequency and downsizing. Therefore, we constr uct transmitting timing calculation unit by FPGA which is implemented Ce ntral Processing Unit (CPU) core. The constructed CPU core can be handle d almost in the same way as a normal microcomputer. As a result of the e valuation, it is found that the constructed CPU core as a foothold in So C implementation of the transmission timing control system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SS-CDMA / FPGA / CPU |
| Paper # | SR2018-60 |
| Date of Issue | 2018-10-23 (SR) |
| Conference Information | |
| Committee | SR |
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| Conference Date | 2018/10/30(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Mandarin Hotel, Bangkok, Thailand |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | SmartCom2018 |
| Chair | Kenta Umebayashi(Tokyo Univ. of Agric. and Tech.) |
| Vice Chair | Masayuki Ariyoshi(NEC) / Suguru Kameda(Tohoku Univ.) |
| Secretary | Masayuki Ariyoshi(NICT) / Suguru Kameda(ATR) |
| Assistant | Gia Khanh Tran(Tokyo Inst. of Tech.) / Syusuke Narieda(Mie Univ.) / Koji Ohshima(Kozo Keikaku Engineering) / Mai Ohta(Fukuoka Univ.) / Teppei Oyama(Fujitsu Lab.) |
| Paper Information | |
| Registration To | Technical Committee on Smart Radio |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Transmitting Timing Calculation Unit with CPU on FPGA for QZSS Short Message SS-CDMA Communication |
| Sub Title (in English) | |
| Keyword(1) | SS-CDMA |
| Keyword(2) | FPGA |
| Keyword(3) | CPU |
| 1st Author's Name | Hiroshi Oguma |
| 1st Author's Affiliation | National Institute of Technology, Toyama College(NIT, Toyama) |
| 2nd Author's Name | Rei Kawai |
| 2nd Author's Affiliation | National Institute of Technology, Toyama College(NIT, Toyama) |
| 3rd Author's Name | Takeshi Asai |
| 3rd Author's Affiliation | Next Dimension Co. Ltd.(Next Dimension Co. Ltd.) |
| 4th Author's Name | Mizuki Motoyoshi |
| 4th Author's Affiliation | Tohoku University(Tohoku University) |
| 5th Author's Name | Mizuki Motoyoshi |
| 5th Author's Affiliation | Tohoku University(Tohoku University) |
| 6th Author's Name | Suguru Kameda |
| 6th Author's Affiliation | Tohoku University(Tohoku University) |
| Date | 2018-10-30 |
| Paper # | SR2018-60 |
| Volume (vol) | vol.118 |
| Number (no) | SR-274 |
| Page | pp.pp.5-6(SR), |
| #Pages | 2 |
| Date of Issue | 2018-10-23 (SR) |