| Presentation | 2018-09-18 Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada, Keiji Miura, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to represent machine learning algorithms as data flow graph and to embed data flow structure on hardware platforms as an approach to efficiently design machine learning accelerators. In this study, we present to implement hardware accelerators for (i) Topological Data Analysis and (ii) Reinforcement Learning by focusing on their data flow representation. First, we briefly review the previous works on data flow representation of machine learning algorithms and their hardware implementation. Second, as a case study, we represent each algorithm of Topological Data Analysis and Reinforcement Learning as a data flow graph, and their hardware implementation based on the data flow graph. Finally, we show that machine learning accelerators can be efficiently designed by using MATLAB/Simulink and HDL Coder, which is a tool that graphically expresses data flow and generates HDL according to computation of various degrees of abstraction. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Machine Learning / Hardware Accelerator / Data Flow Graph / Field-Programmable Gate Array (FPGA) / Hardware Description Language |
| Paper # | RECONF2018-32 |
| Date of Issue | 2018-09-10 (RECONF) |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2018/9/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | LINE Fukuoka Cafe Space |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Chair | Masato Motomura(Hokkaido Univ.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Data Flow Representation and its Applications to Machine Learning Accelerator |
| Sub Title (in English) | |
| Keyword(1) | Machine Learning |
| Keyword(2) | Hardware Accelerator |
| Keyword(3) | Data Flow Graph |
| Keyword(4) | Field-Programmable Gate Array (FPGA) |
| Keyword(5) | Hardware Description Language |
| 1st Author's Name | Kazuki Nakada |
| 1st Author's Affiliation | Tsukuba University of Technology(Tsukuba Univ. of Tech.) |
| 2nd Author's Name | Keiji Miura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| Date | 2018-09-18 |
| Paper # | RECONF2018-32 |
| Volume (vol) | vol.118 |
| Number (no) | RECONF-215 |
| Page | pp.pp.73-78(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-09-10 (RECONF) |