Presentation 2018-08-08
Baisic analysis for fault torelance of paralelled back converters
Hirotaka Kanzaki, Toshimichi Saito,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper studies fault tolerance of a paralleled system of buck conveters by winner-take-all switching rule. The dynamics is described by simple piecewise constant equation. The switching rule can realize multi-phase syncronization automatically. So it is suitable for fault tolerance. Performing basic numerical experiments, we have investigated stability and ripple characteristics for circuit key parameters. We have also investigated stability and ripple characteristics after the accident.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Buck converter / stability / fault tolerance
Paper # NLP2018-62
Date of Issue 2018-08-01 (NLP)

Conference Information
Committee NLP
Conference Date 2018/8/8(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Saiwai-cho Campus, Kagawa Univ.
Topics (in Japanese) (See Japanese page)
Topics (in English) etc.
Chair Norikazu Takahashi(Okayama Univ.)
Vice Chair Hiroaki Kurokawa(Tokyo Univ. of Tech.)
Secretary Hiroaki Kurokawa(Hiroshima Inst. of Tech.)
Assistant Masayuki Kimura(Kyoto Univ.) / Yutaka Shimada(Saitama Univ.)

Paper Information
Registration To Technical Committee on Nonlinear Problems
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Baisic analysis for fault torelance of paralelled back converters
Sub Title (in English)
Keyword(1) Buck converter
Keyword(2) stability
Keyword(3) fault tolerance
1st Author's Name Hirotaka Kanzaki
1st Author's Affiliation Hosei University(HU)
2nd Author's Name Toshimichi Saito
2nd Author's Affiliation Hosei University(HU)
Date 2018-08-08
Paper # NLP2018-62
Volume (vol) vol.118
Number (no) NLP-174
Page pp.pp.47-50(NLP),
#Pages 4
Date of Issue 2018-08-01 (NLP)