| Presentation | 2018-07-31 Reduction of Indirect Addressing in Parallel-Program Generation for Improving Memory Efficiency on Vector Processor Yujiro Ishida, Masao Okita, Kenichi Hagihara, Fumihiko Ino, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We discuss automatic code generation of a vectorizable program from a large-scale mathematical model. Indirect addressing of array elements is useful to vectorize loops that include irregular memory access patterns. However, vectorizing compilers translate indirect addressing into gather/scatter instructions independent of data placement, resulting in a possible performance bottleneck for memory-intensive programs. In this report, we propose a method that replaces redundant indirect addressing with direct addressing by analyzing access patterns during code generation. Furthermore, out method increase access patterns to be writable in a direct addressing manner by enhancing sequential access. Experimental results on SX-ACE demonstrate that the proposed method accelerates a biophysical simulation program including more than 30 million equations by a factor of 1.4. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SX-ACE / Data placement / Auto-vectorization / DSL |
| Paper # | CPSY2018-20 |
| Date of Issue | 2018-07-23 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2018/7/30(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto City International Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Chair | Koji Nakano(Hiroshima Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Masahiro Goshima(NII) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Hiroshi Takahashi(Tokyo Inst. of Tech.) / (Nihon Univ.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of Indirect Addressing in Parallel-Program Generation for Improving Memory Efficiency on Vector Processor |
| Sub Title (in English) | |
| Keyword(1) | SX-ACE |
| Keyword(2) | Data placement |
| Keyword(3) | Auto-vectorization |
| Keyword(4) | DSL |
| 1st Author's Name | Yujiro Ishida |
| 1st Author's Affiliation | Osaka University(Osaka Univ.) |
| 2nd Author's Name | Masao Okita |
| 2nd Author's Affiliation | Osaka University(Osaka Univ.) |
| 3rd Author's Name | Kenichi Hagihara |
| 3rd Author's Affiliation | Osaka University(Osaka Univ.) |
| 4th Author's Name | Fumihiko Ino |
| 4th Author's Affiliation | Osaka University(Osaka Univ.) |
| Date | 2018-07-31 |
| Paper # | CPSY2018-20 |
| Volume (vol) | vol.118 |
| Number (no) | CPSY-165 |
| Page | pp.pp.115-120(CPSY), |
| #Pages | 6 |
| Date of Issue | 2018-07-23 (CPSY) |