| Presentation | 2018-07-30 Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet Yosuke Yanai, Takeshi Matsuya, Yohei Kuga, Tokusashi Yuta, Jun Murai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing environment typified by Intel DPDK realizes high-speed packet processing in a 10 G / 100 G Ethernet environment using a high clock and multi-core CPU. In this proposed function extension, we aim to realize high-speed packet processing with single core and low clock by connecting 1024 bit wide data path that exchanges data with Ethernet PHY to CPU. In this paper, we implemented 32bit RISC-V processor and extension of our proposed method using FPGA. In the evaluation, we confirmed that it is possible to process packets with throughput of 99.1% with respect to the line rate of 10 G Ethernet while processing part of routing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RISC-V / Processor / Architecture / Packet processing / Network |
| Paper # | CPSY2018-15 |
| Date of Issue | 2018-07-23 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2018/7/30(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto City International Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Chair | Koji Nakano(Hiroshima Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Masahiro Goshima(NII) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Hiroshi Takahashi(Tokyo Inst. of Tech.) / (Nihon Univ.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet |
| Sub Title (in English) | |
| Keyword(1) | RISC-V |
| Keyword(2) | Processor |
| Keyword(3) | Architecture |
| Keyword(4) | Packet processing |
| Keyword(5) | Network |
| 1st Author's Name | Yosuke Yanai |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Takeshi Matsuya |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Yohei Kuga |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| 4th Author's Name | Tokusashi Yuta |
| 4th Author's Affiliation | Keio University(Keio Univ.) |
| 5th Author's Name | Jun Murai |
| 5th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2018-07-30 |
| Paper # | CPSY2018-15 |
| Volume (vol) | vol.118 |
| Number (no) | CPSY-165 |
| Page | pp.pp.33-38(CPSY), |
| #Pages | 6 |
| Date of Issue | 2018-07-23 (CPSY) |