| Presentation | 2018-06-14 Area Efficient Multiply-Accumulate Circuit Using Stochastic Computing for Neural Network Hardware Kenta Nagura, Masayuki Hiromoto, Takashi Sato, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Neural network, which is an accurate and general-purpose machine learning method, is attracting greater attention in recent years. Due to the heavy computational load required in both learning and inference, the circuit area and power consumption become large when the neural network is implemented on a hardware. To improve calculation efficiency, we propose to apply stochastic computing (SC) in which the numerical numbers are represented by the number of 1's in a bit sequence. In this paper, we propose a new multiply-accumulate circuit (MAC) using SC, which is a heavily repeated calculation in neural network algorithms. Through experiments, we show the proposed MAC circuit greatly improves the accuracy of the calculation compared with an existing MAC circuit using SC of equal circuit area and power. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | neural network / multiply-accumulate circuit / image recognition / stochastic computing |
| Paper # | CAS2018-15,VLD2018-18,SIP2018-35,MSS2018-15 |
| Date of Issue | 2018-06-07 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | CAS / SIP / MSS / VLD |
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| Conference Date | 2018/6/14(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System and Signal Processing, etc |
| Chair | Hideaki Okazaki(Shonan Inst. of Tech.) / Shogo Muramatsu(Niigata Univ.) / Morikazu Nakamura(Univ. of Ryukyus) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Taizo Yamawaki(Hitachi) / Naoyuki Aikawa(TUS) / Kazunori Hayashi(Osaka City Univ) / Shigemasa Takai(Osaka Univ.) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Taizo Yamawaki(Shonan Inst. of Tech.) / Naoyuki Aikawa(Hitachi) / Kazunori Hayashi(Takushoku Univ.) / Shigemasa Takai(Hiroshima Univ.) / Nozomu Togawa(Toshiba) |
| Assistant | Motoi Yamaguchi(Renesas Electronics) / / Hideki Kinjo(Okinawa Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area Efficient Multiply-Accumulate Circuit Using Stochastic Computing for Neural Network Hardware |
| Sub Title (in English) | |
| Keyword(1) | neural network |
| Keyword(2) | multiply-accumulate circuit |
| Keyword(3) | image recognition |
| Keyword(4) | stochastic computing |
| 1st Author's Name | Kenta Nagura |
| 1st Author's Affiliation | Kyoto University(Kyoto Univ) |
| 2nd Author's Name | Masayuki Hiromoto |
| 2nd Author's Affiliation | Kyoto University(Kyoto Univ) |
| 3rd Author's Name | Takashi Sato |
| 3rd Author's Affiliation | Kyoto University(Kyoto Univ) |
| Date | 2018-06-14 |
| Paper # | CAS2018-15,VLD2018-18,SIP2018-35,MSS2018-15 |
| Volume (vol) | vol.118 |
| Number (no) | CAS-82,VLD-83,SIP-84,MSS-85 |
| Page | pp.pp.81-86(CAS), pp.81-86(VLD), pp.81-86(SIP), pp.81-86(MSS), |
| #Pages | 6 |
| Date of Issue | 2018-06-07 (CAS, VLD, SIP, MSS) |