Presentation 2018-06-14
Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
Tatsuki Hoshiba, Yukihide Kohira,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In recent LSI design, it is difficult to obtain a placement that satisfies both design constraints and specifications due to increase of circuit size and progress of manufacturing technology. Analytical placement methods have been proposed to obtain a placement with short wire length for placement problem with many blocks. Analytical placement methods formulate placement problem to mathematical programming problems and obtain a placement by using their solvers. The analytical placement methods have advantages such that conditions and constraints are added easily and existing solvers for mathematical programming problems can be utilized. The analytical methods using quasi-Newton method have good convergence and they can be applied to problems with large scale circuits. However, since the analytical placement methods using quasi-Newton method depend on initial placements, they are repeatedly applied to obtain a placement with short wire length. In this paper, we propose a placement method that makes a machine learning model to predict wire length of the placement obtained by an analytical placement method using quasi-Newton method from a placement, predicts wire length after applying the analytical placement method using quasi-Newton method by using the model, and applies the analytical placement method using quasi-Newton method to only placements whose predicted wire lengths are short. We evaluate effectiveness of the proposed method in computational experiments.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Placement problem / analytical placement / machine learning / wire length prediction
Paper # CAS2018-14,VLD2018-17,SIP2018-34,MSS2018-14
Date of Issue 2018-06-07 (CAS, VLD, SIP, MSS)

Conference Information
Committee CAS / SIP / MSS / VLD
Conference Date 2018/6/14(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Hokkaido Univ. (Frontier Research in Applied Sciences Build.)
Topics (in Japanese) (See Japanese page)
Topics (in English) System and Signal Processing, etc
Chair Hideaki Okazaki(Shonan Inst. of Tech.) / Shogo Muramatsu(Niigata Univ.) / Morikazu Nakamura(Univ. of Ryukyus) / Noriyuki Minegishi(Mitsubishi Electric)
Vice Chair Taizo Yamawaki(Hitachi) / Naoyuki Aikawa(TUS) / Kazunori Hayashi(Osaka City Univ) / Shigemasa Takai(Osaka Univ.) / Nozomu Togawa(Waseda Univ.)
Secretary Taizo Yamawaki(Shonan Inst. of Tech.) / Naoyuki Aikawa(Hitachi) / Kazunori Hayashi(Takushoku Univ.) / Shigemasa Takai(Hiroshima Univ.) / Nozomu Togawa(Toshiba)
Assistant Motoi Yamaguchi(Renesas Electronics) / / Hideki Kinjo(Okinawa Univ.)

Paper Information
Registration To Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
Sub Title (in English)
Keyword(1) Placement problem
Keyword(2) analytical placement
Keyword(3) machine learning
Keyword(4) wire length prediction
1st Author's Name Tatsuki Hoshiba
1st Author's Affiliation The University of Aizu(Univ. of Aizu)
2nd Author's Name Yukihide Kohira
2nd Author's Affiliation The University of Aizu(Univ. of Aizu)
Date 2018-06-14
Paper # CAS2018-14,VLD2018-17,SIP2018-34,MSS2018-14
Volume (vol) vol.118
Number (no) CAS-82,VLD-83,SIP-84,MSS-85
Page pp.pp.75-80(CAS), pp.75-80(VLD), pp.75-80(SIP), pp.75-80(MSS),
#Pages 6
Date of Issue 2018-06-07 (CAS, VLD, SIP, MSS)