| Presentation | 2018-05-25 Design of an MTJ-Based Multi-Functional Lookup Table Circuit Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A multi-functional nonvolatile lookup table (LUT) circuit is described using a magnetic tunnel junction (MTJ) and CMOS hybrid circuit design. By utilizing a data addressing in the LUT circuit, the state of the MTJ device is serially read and written, which results in the shift-register (SR) function with minimum write access. Moreover, since the decoder for the LUT function can also be used for the data addressing, the hardware overhead is quite small. In fact, the effective area of the proposed 6-input LUT circuit and power consumption for the SR function are reduced by 53% and 88% compared to those of the SRAM-based implementation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Field-Programmable Gate Array (FPGA) / Magnetic Tunnel Junction (MTJ) Device / Lookup Table (LUT) Circuit |
| Paper # | RECONF2018-12 |
| Date of Issue | 2018-05-17 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2018/5/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | GATE CITY OHSAKI |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Deep Learning, Reconfigurable Systems, etc. |
| Chair | Masato Motomura(Hokkaido Univ.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of an MTJ-Based Multi-Functional Lookup Table Circuit |
| Sub Title (in English) | |
| Keyword(1) | Field-Programmable Gate Array (FPGA) |
| Keyword(2) | Magnetic Tunnel Junction (MTJ) Device |
| Keyword(3) | Lookup Table (LUT) Circuit |
| 1st Author's Name | Daisuke Suzuki |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Takahiro Oka |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Takahiro Hanyu |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2018-05-25 |
| Paper # | RECONF2018-12 |
| Volume (vol) | vol.118 |
| Number (no) | RECONF-63 |
| Page | pp.pp.59-64(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-05-17 (RECONF) |