| Presentation | 2018-05-24 Prototyping of Dynamic Reconfiguration System to Execute Fallback Function Designed by High Level Synthesis Teruaki Sakata, Teppei Hirotsu, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We developed the architecture to execute a fallback operation when a failure occurred. In this research, we designed FPGA hardware and CPU software by high level synthesis from the common behavioral description including pragmas. In case of FPGA failure, the CPU continues fallback process by release resources and the reconfiguration from lock-step to multi-core. We made a prototype of this system with a counter function on SoC-FPGA board. The designed FPGA bitstream size of the function was 25.2MB and the CPU binary size was 1.3KB. The transition time from the normal to the fallback operation was about 1.13ms, and the recovery time from the fallback to the normal operation with reconfiguring FPGA was about 120ms. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High Level Synthesis / FPGA / CPU / Dynamic Reconfiguration / Fallback |
| Paper # | RECONF2018-3 |
| Date of Issue | 2018-05-17 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2018/5/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | GATE CITY OHSAKI |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Deep Learning, Reconfigurable Systems, etc. |
| Chair | Masato Motomura(Hokkaido Univ.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Prototyping of Dynamic Reconfiguration System to Execute Fallback Function Designed by High Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | High Level Synthesis |
| Keyword(2) | FPGA |
| Keyword(3) | CPU |
| Keyword(4) | Dynamic Reconfiguration |
| Keyword(5) | Fallback |
| 1st Author's Name | Teruaki Sakata |
| 1st Author's Affiliation | Hitachi, Ltd.(Hitachi) |
| 2nd Author's Name | Teppei Hirotsu |
| 2nd Author's Affiliation | Hitachi, Ltd.(Hitachi) |
| Date | 2018-05-24 |
| Paper # | RECONF2018-3 |
| Volume (vol) | vol.118 |
| Number (no) | RECONF-63 |
| Page | pp.pp.13-18(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-05-17 (RECONF) |