| Presentation | 2018-05-16 Non-volatile Power Gating for Data Cache with Dynamic Line-selection Sosuke Akiba, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is a technique of reducing the leakage power of the cache while keeping the stored data by applying the nonvolatile element MTJ to the SRAM that is constituting the cache. However, when PG is applied to data cache with Write-back writing system, there is a problem that information to be written in the main memory is lost and cache coherency cannot be maintained. In this paper, we examine the NVPG method applicable to the data cache that selects storage line based on decay miss density. Moreover, we evaluate the reduction of leakage power by the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power-Gating / MTJ / data cache / Cache decay |
| Paper # | VLD2018-2 |
| Date of Issue | 2018-05-09 (VLD) |
| Conference Information | |
| Committee | VLD / IPSJ-SLDM |
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| Conference Date | 2018/5/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Yutaka Tamiya(Fujitsu Laboratories) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Non-volatile Power Gating for Data Cache with Dynamic Line-selection |
| Sub Title (in English) | |
| Keyword(1) | Power-Gating |
| Keyword(2) | MTJ |
| Keyword(3) | data cache |
| Keyword(4) | Cache decay |
| 1st Author's Name | Sosuke Akiba |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| Date | 2018-05-16 |
| Paper # | VLD2018-2 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-29 |
| Page | pp.pp.19-24(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-05-09 (VLD) |