Presentation 2018-04-13
AES-OTR Hardware Architecture and Its Evaluation
Rei Ueno, Noafumi Homma, Tomonori Iida, Kazuhiko Minematsu,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper reports a hardware implementation of AES-OTR, an authenticated encryption schemes based on AES. AES-OTR is a candidate of CAESAR competition, an international competition for authenticated encryption. We propose a compact multi-core architecture for AES-OTR which utilizes its parallelizability and inverse-freeness property (i.e. the decryption logic of AES is not needed), and show implementation results on ASIC and FPGA.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Authenticated Encryption / AES-OTR / Hardware Architecture
Paper # HWS2018-4
Date of Issue 2018-04-06 (HWS)

Conference Information
Committee HWS
Conference Date 2018/4/13(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Tsutomu Matsumoto(Yokohama National Univ.)
Vice Chair Shinichi Kawamura(Toshiba Corporation) / Makoto Ikeda(Univ. of Tokyo)
Secretary Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM)
Assistant

Paper Information
Registration To Technical Committee on Hardware Security
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) AES-OTR Hardware Architecture and Its Evaluation
Sub Title (in English)
Keyword(1) Authenticated Encryption
Keyword(2) AES-OTR
Keyword(3) Hardware Architecture
1st Author's Name Rei Ueno
1st Author's Affiliation Tohoku University(Tohoku Univ.)
2nd Author's Name Noafumi Homma
2nd Author's Affiliation Tohoku University(Tohoku Univ.)
3rd Author's Name Tomonori Iida
3rd Author's Affiliation Y.D.K.CO., LTD(YDK)
4th Author's Name Kazuhiko Minematsu
4th Author's Affiliation NEC Corporation(NEC)
Date 2018-04-13
Paper # HWS2018-4
Volume (vol) vol.118
Number (no) HWS-3
Page pp.pp.17-21(HWS),
#Pages 5
Date of Issue 2018-04-06 (HWS)