| Presentation | 2018-04-20 [Invited Lecture] A new core transistor equipped with NVM functionality without using any emerging memory materials Yasuhiro Taniguchi, Shoji Yoshida, Owada Fukuo, Yutaka Shinagawa, Hideo Kasai, Lin Jia You, Wei I Huan, Daisuke Okada, Koichi Nagasawa, Kosuke Okuyama, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A tri-gate core transistor which has nonvolatile memory [NVM] functionality in midsection of a logic transistor gate was developed on 90nm CMOS process and demonstrated its functionality and validity. It is possible to be embedded into logic blocks seamlessly. Program and Erase [P/E] operation of the nonvolatile core transistor [NV Core Trs] is performed with ultra-low current by employing FN tunneling, and it is controlled by the circuits configured only with logic devices. No high voltage transistor is necessary in the logic blocks, and the area of peripheral circuits become extremely small. Integration of memory and logic becomes quite easy, and thus, some of new architecture and applications are possible to create without using any emerging memory materials. Proposed examples are ultra-high speed nonvolatile RAM [NVRAM] with direct conjunction of NV Core Trs and SRAM cell, and highly sophisticated secure NVM. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | nonvolatile / memory / NVRAM / NVSRAM / core / SONOS / scalability |
| Paper # | ICD2018-7 |
| Date of Issue | 2018-04-12 (ICD) |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2018/4/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hideto Hidaka(Renesas) |
| Vice Chair | Makoto Nagata(Kobe Univ.) |
| Secretary | Makoto Nagata(Univ. of Tokyo) |
| Assistant | Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Lecture] A new core transistor equipped with NVM functionality without using any emerging memory materials |
| Sub Title (in English) | |
| Keyword(1) | nonvolatile |
| Keyword(2) | memory |
| Keyword(3) | NVRAM |
| Keyword(4) | NVSRAM |
| Keyword(5) | core |
| Keyword(6) | SONOS |
| Keyword(7) | scalability |
| 1st Author's Name | Yasuhiro Taniguchi |
| 1st Author's Affiliation | Floadia Corporation(Floadia) |
| 2nd Author's Name | Shoji Yoshida |
| 2nd Author's Affiliation | Floadia Corporation(Floadia) |
| 3rd Author's Name | Owada Fukuo |
| 3rd Author's Affiliation | Floadia Corporation(Floadia) |
| 4th Author's Name | Yutaka Shinagawa |
| 4th Author's Affiliation | Floadia Corporation(Floadia) |
| 5th Author's Name | Hideo Kasai |
| 5th Author's Affiliation | Floadia Corporation(Floadia) |
| 6th Author's Name | Lin Jia You |
| 6th Author's Affiliation | Powerchip Technology Corporation(PTC) |
| 7th Author's Name | Wei I Huan |
| 7th Author's Affiliation | Powerchip Technology Corporation(PTC) |
| 8th Author's Name | Daisuke Okada |
| 8th Author's Affiliation | Floadia Corporation(Floadia) |
| 9th Author's Name | Koichi Nagasawa |
| 9th Author's Affiliation | Floadia Corporation(Floadia) |
| 10th Author's Name | Kosuke Okuyama |
| 10th Author's Affiliation | Floadia Corporation(Floadia) |
| Date | 2018-04-20 |
| Paper # | ICD2018-7 |
| Volume (vol) | vol.118 |
| Number (no) | ICD-10 |
| Page | pp.pp.23-27(ICD), |
| #Pages | 5 |
| Date of Issue | 2018-04-12 (ICD) |