Presentation 2018-04-20
[Invited Talk] Memory LSI using crystalline oxide semiconductor FET
Jun Koyama, Takako Seki, Yuto Yakubo, Satoru Ohshita, Kazuma Furutani, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda, Masahiro Fujita, Shunpei Yamazaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) FETs fabricated with a c-axis aligned crystalline In-Ga-Zn oxide semiconductor (CAAC-IGZO) have an extremely low off-state current of 6 yA/?m at 85?C. Use of this FET enables memory circuits with extremely low power consumption. SEL has developed a 1kbit n-channel only memory module including dynamic logic circuits using a 60nm crystalline oxide semiconductor fabrication technology. This memory module achieves write pulse width and read access time of 20 ns and 45 ns, respectively, at VDD ? 3.3 V. The write and read energies are 97.9 pJ and 123.6 pJ, respectively, and it endures 1014 write cycles.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Crystalline Oxide Semiconductor / CAAC-IGZO / off-state current / n-channel only memory module / dynamic logic circuits
Paper # ICD2018-12
Date of Issue 2018-04-12 (ICD)

Conference Information
Committee ICD
Conference Date 2018/4/19(2days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Hideto Hidaka(Renesas)
Vice Chair Makoto Nagata(Kobe Univ.)
Secretary Makoto Nagata(Univ. of Tokyo)
Assistant Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Invited Talk] Memory LSI using crystalline oxide semiconductor FET
Sub Title (in English)
Keyword(1) Crystalline Oxide Semiconductor
Keyword(2) CAAC-IGZO
Keyword(3) off-state current
Keyword(4) n-channel only memory module
Keyword(5) dynamic logic circuits
1st Author's Name Jun Koyama
1st Author's Affiliation Semiconductor Energy Laboratory(SEL)
2nd Author's Name Takako Seki
2nd Author's Affiliation Semiconductor Energy Laboratory(SEL)
3rd Author's Name Yuto Yakubo
3rd Author's Affiliation Semiconductor Energy Laboratory(SEL)
4th Author's Name Satoru Ohshita
4th Author's Affiliation Semiconductor Energy Laboratory(SEL)
5th Author's Name Kazuma Furutani
5th Author's Affiliation Semiconductor Energy Laboratory(SEL)
6th Author's Name Takahiko Ishizu
6th Author's Affiliation Semiconductor Energy Laboratory(SEL)
7th Author's Name Tomoaki Atsumi
7th Author's Affiliation Semiconductor Energy Laboratory(SEL)
8th Author's Name Yoshinori Ando
8th Author's Affiliation Semiconductor Energy Laboratory(SEL)
9th Author's Name Daisuke Matsubayashi
9th Author's Affiliation Semiconductor Energy Laboratory(SEL)
10th Author's Name Kiyoshi Kato
10th Author's Affiliation Semiconductor Energy Laboratory(SEL)
11th Author's Name Takashi Okuda
11th Author's Affiliation Semiconductor Energy Laboratory(SEL)
12th Author's Name Masahiro Fujita
12th Author's Affiliation The University of Tokyo(The Univ. of Tokyo)
13th Author's Name Shunpei Yamazaki
13th Author's Affiliation Semiconductor Energy Laboratory(SEL)
Date 2018-04-20
Paper # ICD2018-12
Volume (vol) vol.118
Number (no) ICD-10
Page pp.pp.47-52(ICD),
#Pages 6
Date of Issue 2018-04-12 (ICD)