| Presentation | 2018-03-01 Implementation and Evaluation of MCTS-Based Parallel Prefix Adder Synthesis Taeko Matsunaga, Yusuke Matsunaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
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| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
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| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and Evaluation of MCTS-Based Parallel Prefix Adder Synthesis |
| Sub Title (in English) | |
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| 1st Author's Name | Taeko Matsunaga |
| 1st Author's Affiliation | Nippon Bunri University(NBU) |
| 2nd Author's Name | Yusuke Matsunaga |
| 2nd Author's Affiliation | Kyushu University(Kyushu Univ.) |
| Date | 2018-03-01 |
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| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.-(), |
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