| Presentation | 2018-03-01 A Concept of DNN Framework for Embedded System Using FPGA Ryota Yamamoto, Takuya Okamoto, Shinya Honda, Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto, Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system. For an embedded systems, because its implementation may have severe restrictions on memory, speed, and real-time property. On the other hand, an FPGA can be configured a flexible logic circuit for specializing calculations. It can calculate faster than CPUs and lower power than GPUs. This study, we consider a DNN framework for an embedded system using an FPGA. Our framework has a generator for C language source code for high-level synthesis then configure FPGA using trained date generated by existent DNN framework. This paper, we describe a concept of the framework and the relationship between our study and related work. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Deep Learning / FPGA / High-Level Synthesis |
| Paper # | VLD2017-117 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Concept of DNN Framework for Embedded System Using FPGA |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | FPGA |
| Keyword(3) | High-Level Synthesis |
| 1st Author's Name | Ryota Yamamoto |
| 1st Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 2nd Author's Name | Takuya Okamoto |
| 2nd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 3rd Author's Name | Shinya Honda |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 4th Author's Name | Qian Zhao |
| 4th Author's Affiliation | University of Hyogo(Hyogo Univ.) |
| 5th Author's Name | Toki Matsumoto |
| 5th Author's Affiliation | University of Hyogo(Hyogo Univ.) |
| 6th Author's Name | Yukikazu Nakamoto |
| 6th Author's Affiliation | University of Hyogo(Hyogo Univ.) |
| 7th Author's Name | Tamotsu Sakai |
| 7th Author's Affiliation | NEC Corporation Inc.(NEC) |
| 8th Author's Name | Tetsuya Aoyama |
| 8th Author's Affiliation | NEC Corporation Inc.(NEC) |
| 9th Author's Name | Kazutoshi Wakabayashi |
| 9th Author's Affiliation | NEC Corporation Inc.(NEC) |
| Date | 2018-03-01 |
| Paper # | VLD2017-117 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.169-174(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |