| Presentation | 2018-03-02 Energy Reduction of Standard-Cell Memory Exploiting Selective Activation Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | On-chip memories have a large impact on energy-efficiency of LSI circuits. This paper discusses energy-efficient on-chip memory structures which are suitable for Standard-Cell Memories (SCMs). When SCMs perform write operation or readout operation, their bit-lines are charged or discharged. Clock buffers in their clock tree are also activated in write operation. Since dynamic energy consumed at the bit-lines and the clock buffers are considerably large, this paper proposes circuit structures where (1) clock gating circuits are inserted into the clock tree, and (2) the bit-lines are splitted using demultiplexers. The structure enables to selectively activate the clock tree and the bit-lines, which effectively reduces the dynamic energy consumption in write opretion. Post layout simulation results using a 65-nm SOTB process technology show that the proposed SCM achieves 59% less energy consumption than an SCM with a convetional structure. Measurement results of a test chip fabricated in the same process also shows that the proposed SCM achieves 67% less energy consumption than the 6T SRAM. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Standard-Cell Memory (SCM) / low-voltage operation / on-chip memory / selective activation |
| Paper # | VLD2017-124 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Energy Reduction of Standard-Cell Memory Exploiting Selective Activation |
| Sub Title (in English) | |
| Keyword(1) | Standard-Cell Memory (SCM) |
| Keyword(2) | low-voltage operation |
| Keyword(3) | on-chip memory |
| Keyword(4) | selective activation |
| 1st Author's Name | Jun Shiomi |
| 1st Author's Affiliation | Kyoto University(Kyoto Univ.) |
| 2nd Author's Name | Tohru Ishihara |
| 2nd Author's Affiliation | Kyoto University(Kyoto Univ.) |
| 3rd Author's Name | Hidetoshi Onodera |
| 3rd Author's Affiliation | Kyoto University(Kyoto Univ.) |
| Date | 2018-03-02 |
| Paper # | VLD2017-124 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.211-216(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |