| Presentation | 2018-03-01 An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit Yuki Arai, Shuji Tsukiyama, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In general-synchronous framework, the clock signal is distributed to each register in optimal individual timing, so that the clock period can be less than the critical delay of a combinatorial circuit. In order to achieve the minimum clock period, we must increase the shortest delay of a combinatorial circuit optimally. This technique is called delay insertion and several papers have been published. However, due to the process variability, delay values may vary chip-by-chip, and hence we must consider delay insertion in a sort of statistical manner. In such a statistical design approach, if delay insertion techniques are complicated, it may be hard to devise a statistical delay insertion algorithm. Therefore, in this paper, we propose a simple heuristic method for delay insertion and evaluate its performance. This method repeats a graph reduction technique, and operations used in the technique are addition and maximum only, similar to statistical static timing analysis. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | graph reduction technique / minimum clock period / delay insertion / general-synchronous circuit / performance evaluation |
| Paper # | VLD2017-110 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit |
| Sub Title (in English) | |
| Keyword(1) | graph reduction technique |
| Keyword(2) | minimum clock period |
| Keyword(3) | delay insertion |
| Keyword(4) | general-synchronous circuit |
| Keyword(5) | performance evaluation |
| 1st Author's Name | Yuki Arai |
| 1st Author's Affiliation | Chuo University(Chuo Univ.) |
| 2nd Author's Name | Shuji Tsukiyama |
| 2nd Author's Affiliation | Chuo University(Chuo Univ.) |
| Date | 2018-03-01 |
| Paper # | VLD2017-110 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.127-132(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |