| Presentation | 2018-03-01 A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit Takuya Okamoto, Ryota Yamamoto, Shinya Honda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Today, Deep Neural Network (DNN) is utilized in various ?elds. There is a demand for deep learning in the ?eld of embedded systems. On the other hand, DNN classi?er on the system requires memory-saving and real?time property. Therefore, we target to FPGA and con?gure a classi?er for deep learning on FPGA with high-level synthesis (HLS) tool. To satisfy the system requirement, we consider an e?ective C source code description for high level synthesis. Speci?cally, our proposed accelerators are following: pipelining, prefetching, packing and caching. Compared to the original implementation, the execution speed by each accelerator was 2.3 times, 2.8 times, 5.7 times, 3.3 times faster, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / DNN / High Level Synthesis |
| Paper # | VLD2017-116 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | DNN |
| Keyword(3) | High Level Synthesis |
| 1st Author's Name | Takuya Okamoto |
| 1st Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 2nd Author's Name | Ryota Yamamoto |
| 2nd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 3rd Author's Name | Shinya Honda |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| Date | 2018-03-01 |
| Paper # | VLD2017-116 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.163-168(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |