| Presentation | 2018-02-28 Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis Daisuke Ishikawa, Kenshu Seto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We develop a loop flattening tool for designing hardware with high level synthesis. When loop pipelining is applied to nested for-loops, the overhead in the number of execution cycles occurs. Loop flattening is one of the ways to reduce this overhead. At least three loop flattening method exists, so it is necessary to manually select the optimal one for a given nested loop. In order to facilitate this selection, we propose an automatic flow of loop flattening. In this paper, we experimentally evaluate the three loop flattening method and derive the criteria to select the best loop flattening method from the three for a given loop nest. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-Level Synthesis / Loop Flattening / LLVM |
| Paper # | VLD2017-97 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis |
| Keyword(2) | Loop Flattening |
| Keyword(3) | LLVM |
| 1st Author's Name | Daisuke Ishikawa |
| 1st Author's Affiliation | Tokyo City University(TCU) |
| 2nd Author's Name | Kenshu Seto |
| 2nd Author's Affiliation | Tokyo City University(TCU) |
| Date | 2018-02-28 |
| Paper # | VLD2017-97 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.49-54(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |