Presentation 2018-03-08
Development of Attaching Security Enhancement Device
Kenji Toda, Kazukuni Kobara, Hirofumi Sakane,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A security enhancement device for information processing devices such as PCs and servers are developed. By attaching the enhancement device into peripheral I/O ports between a PC motherboard and peripheral devices, access control such as read / write detection or protection, of specified files and disk regions are achieved. The device is based on FPGA and having SATA, USB, DVI, LAN ports. Users can operate the devices safely based on direct control on them: using a keyboard and a mouse based on display output. This manuscript describes its functions and discusses the use of the device.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Peripheral I/O relay / disk I/O / access control / security enhancement device / FPGA
Paper # CPSY2017-150,DC2017-106
Date of Issue 2018-02-28 (CPSY, DC)

Conference Information
Committee CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2018/3/7(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinoshima Bunka-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) ETNET2018
Chair Koji Nakano(Hiroshima Univ.) / Michiko Inoue(NAIST) / Kiyoharu Hamaguchi(Shimane Univ.) / / Masahiro Goshima(NII)
Vice Chair Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Satoshi Fukumoto(Tokyo Metropolitan Univ.)
Secretary Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) / (Panasonic) / (Kochi Univ. of Tech.)
Assistant Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Masayuki Arai(Nihon Univ.)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Attaching Security Enhancement Device
Sub Title (in English)
Keyword(1) Peripheral I/O relay
Keyword(2) disk I/O
Keyword(3) access control
Keyword(4) security enhancement device
Keyword(5) FPGA
1st Author's Name Kenji Toda
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
2nd Author's Name Kazukuni Kobara
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
3rd Author's Name Hirofumi Sakane
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
Date 2018-03-08
Paper # CPSY2017-150,DC2017-106
Volume (vol) vol.117
Number (no) CPSY-479,DC-480
Page pp.pp.281-287(CPSY), pp.281-287(DC),
#Pages 7
Date of Issue 2018-02-28 (CPSY, DC)