| Presentation | 2018-03-08 Design of Memoristor-Logic-Based Check Correction Code Circuit Mamoru Ishizaka, Michihiro Shintani, Michiko inoue, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Resistive RAM (ReRAM) is one of the most promising memory technologies due to its property such as high density, low-power, good-scalability, and non-volatility. However, similar to other memory technologies, the memristor, which is the primitive component of the ReRAM, has also limited write endurance. In the conventional memories, error correcting code (ECC) circuit has been applied to improve the reliability. In this paper, a novel ECC circuit implemented by memristors is proposed. Since the lifetime of the memristor is limited due to the write endurance, the one of the ECC circuit is also limited. In the proposed ECC circuit, the block with high frequent write operation is implemented by CMOS logic. Consequently, the area overhead of the ECC circuit can be reduced. Numerical experimental results demonstrate that the proposed ECC circuit successfully enhance the lifetime of the ReRAM storage system with the additional $5 times 10^5$ write operations while reducing the area overhead impact by 73%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Resistive Random Access Memory / Memristor / Error check and correction code circuit / Reliability |
| Paper # | CPSY2017-146,DC2017-102 |
| Date of Issue | 2018-02-28 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2018/3/7(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinoshima Bunka-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2018 |
| Chair | Koji Nakano(Hiroshima Univ.) / Michiko Inoue(NAIST) / Kiyoharu Hamaguchi(Shimane Univ.) / / Masahiro Goshima(NII) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) / (Panasonic) / (Kochi Univ. of Tech.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Memoristor-Logic-Based Check Correction Code Circuit |
| Sub Title (in English) | |
| Keyword(1) | Resistive Random Access Memory |
| Keyword(2) | Memristor |
| Keyword(3) | Error check and correction code circuit |
| Keyword(4) | Reliability |
| 1st Author's Name | Mamoru Ishizaka |
| 1st Author's Affiliation | National Institute of Technology, Nara College(NITNC) |
| 2nd Author's Name | Michihiro Shintani |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Michiko inoue |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2018-03-08 |
| Paper # | CPSY2017-146,DC2017-102 |
| Volume (vol) | vol.117 |
| Number (no) | CPSY-479,DC-480 |
| Page | pp.pp.257-262(CPSY), pp.257-262(DC), |
| #Pages | 6 |
| Date of Issue | 2018-02-28 (CPSY, DC) |