Presentation 2018-03-07
Optimization of Memory Accesses of Large Scale Graph Analysis Using Multiport and Multibank Memory
Keigo Teramoto, Atsushi Kubota, Tetsuo Hironaka,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Recently, large scale graph analysis is getting important in the development of the Web and social networks. And in the benchmark tests such as the graph500 which evaluates the performance of large scale graph analysis, higher memory access bandwidth is required to achieve high performance. In response to such requirement, HMC (Hybrid Memory Cube) which is a three-dimensional memory provides high memory bandwidth with multiport and multibank access. In this paper, we designed a breadth-first search hardware that optimized memory access for the HMC-FPGA system. This implementation on FPGA achieved 21.9 MTEPS in performance.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) 3D memory / HMC / FPGA / Memory access / Breadth-first search
Paper # CPSY2017-136,DC2017-92
Date of Issue 2018-02-28 (CPSY, DC)

Conference Information
Committee CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2018/3/7(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinoshima Bunka-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) ETNET2018
Chair Koji Nakano(Hiroshima Univ.) / Michiko Inoue(NAIST) / Kiyoharu Hamaguchi(Shimane Univ.) / / Masahiro Goshima(NII)
Vice Chair Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Satoshi Fukumoto(Tokyo Metropolitan Univ.)
Secretary Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) / (Panasonic) / (Kochi Univ. of Tech.)
Assistant Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Masayuki Arai(Nihon Univ.)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optimization of Memory Accesses of Large Scale Graph Analysis Using Multiport and Multibank Memory
Sub Title (in English)
Keyword(1) 3D memory
Keyword(2) HMC
Keyword(3) FPGA
Keyword(4) Memory access
Keyword(5) Breadth-first search
1st Author's Name Keigo Teramoto
1st Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
2nd Author's Name Atsushi Kubota
2nd Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
3rd Author's Name Tetsuo Hironaka
3rd Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
Date 2018-03-07
Paper # CPSY2017-136,DC2017-92
Volume (vol) vol.117
Number (no) CPSY-479,DC-480
Page pp.pp.101-106(CPSY), pp.101-106(DC),
#Pages 6
Date of Issue 2018-02-28 (CPSY, DC)