| Presentation | 2018-02-28 Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Moore's Law has been miniaturizing integrated circuits, whichcan make a lot of high performance devices such as PCs and mobilephones. However, reliability issues have become a significant concern dueto a soft error caused by radiation. The device can recover from thesoft error by restarting because the soft error is atransient error. However, it is a serious problem especiallyfor several devices related to human life. Thus, the research of the soft erroris very important. Leakage current is one of problems in the Internet of Things (IoT) society in recent years. We evaluated a soft error tolerance of twodifference chips with low-power (LP) and low-standby-power (LSTP) transistors respectively. In 65 nm FDSOI process using Ar andKr ions. The measurement results show that the chip with LSTP transistors is 2X stronger against soft errors thanthat with LP transistors. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | soft error / flip-flop / FDSOI / heavy ion / threshold voltage |
| Paper # | VLD2017-104 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
|---|---|
| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage |
| Sub Title (in English) | |
| Keyword(1) | soft error |
| Keyword(2) | flip-flop |
| Keyword(3) | FDSOI |
| Keyword(4) | heavy ion |
| Keyword(5) | threshold voltage |
| 1st Author's Name | Mitsunori Ebara |
| 1st Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 2nd Author's Name | Haruki Maruoka |
| 2nd Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 3rd Author's Name | Kodai Yamada |
| 3rd Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 4th Author's Name | Jun Furuta |
| 4th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 5th Author's Name | Kazutoshi Kobayashi |
| 5th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| Date | 2018-02-28 |
| Paper # | VLD2017-104 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.91-96(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |