| Presentation | 2018-03-02 Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that enables power gating by using magnetic tunnel junction (MTJ). Furthermore, the NVFF that realizes store energy reduction by enabling to verify stored data has been proposed. However, the control to verify is complicated, and it requires to change the operation depending on each application. In this paper, we propose a method and circuit structure enabling the NVFF control by assembly instructions of a reconfigurable accelerator Cool Mega-Array (CMA) using the NVFF enabling to verify. We show the simulation results of the energy consumption when operating the application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low Energy Consumption / Power-Gating / MTJ / Flip-Flop / Cool Mega-Array |
| Paper # | VLD2017-122 |
| Date of Issue | 2018-02-21 (VLD) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2018/2/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / (NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data |
| Sub Title (in English) | |
| Keyword(1) | Low Energy Consumption |
| Keyword(2) | Power-Gating |
| Keyword(3) | MTJ |
| Keyword(4) | Flip-Flop |
| Keyword(5) | Cool Mega-Array |
| 1st Author's Name | Junya Akaike |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 3rd Author's Name | Masaru Kudo |
| 3rd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University(Keio Univ.) |
| 5th Author's Name | Takeharu Ikezoe |
| 5th Author's Affiliation | Keio University(Keio Univ.) |
| 6th Author's Name | Keizo Hiraga |
| 6th Author's Affiliation | Sony Semiconductor Solutions Corporation(Sony SS) |
| 7th Author's Name | Yusuke Shuto |
| 7th Author's Affiliation | Sony Semiconductor Solutions Corporation(Sony SS) |
| 8th Author's Name | Kojiro Yagami |
| 8th Author's Affiliation | Sony Semiconductor Solutions Corporation(Sony SS) |
| Date | 2018-03-02 |
| Paper # | VLD2017-122 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-455 |
| Page | pp.pp.199-204(VLD), |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |