| Presentation | 2018-02-20 Locating Hot Spots with Justification Techniques in a Layout Design Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-speed testing causes excessive IR-drop and delay, resulting in over-testing. In order to avoid over-testing, which directly is related to yield loss, test power reduction and efficient power analysis is required. Since excessive IR-drop does not occur in whole area of LSI, locating an area with high IR-drop is very important. There are two techniques to analyze power such as dynamic one and static one. Dynamic techniques require test vectors and its computational cost is expensive. In this work, we proposed a technique to locate an area with high IR-drop with static technique. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | At-speed testing / test power / over-testing / transition delay test / test generation |
| Paper # | DC2017-80 |
| Date of Issue | 2018-02-13 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2018/2/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Locating Hot Spots with Justification Techniques in a Layout Design |
| Sub Title (in English) | |
| Keyword(1) | At-speed testing |
| Keyword(2) | test power |
| Keyword(3) | over-testing |
| Keyword(4) | transition delay test |
| Keyword(5) | test generation |
| 1st Author's Name | Yudai Kawano |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Kohei Miyase |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Seiji Kajihara |
| 3rd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 4th Author's Name | Xiaoqing Wen |
| 4th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2018-02-20 |
| Paper # | DC2017-80 |
| Volume (vol) | vol.117 |
| Number (no) | DC-444 |
| Page | pp.pp.19-24(DC), |
| #Pages | 6 |
| Date of Issue | 2018-02-13 (DC) |