| Presentation | 2018-02-20 Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | TSV attracts attention as a new implementation method of interconnects between dies in 3DICs. However, faulty TSVs may cause small delay faults because of defects in TSVs such as voids and pinholes during the manufacturing process. We have been proposed a DFT(Design-For-Testability) method for TSVs using a boundary scan circuit with embedded TDC(TDCBS). We proposed the design method for reducing variation of additional delay by reordering delay elements. However, in this method, the wire for forming a loop becomes long compared with other wires. In this paper, we present the design method for reducing the wire length of the feedback wire by reordering delay elements under consideration of a loop. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | small delay fault / TSV / TDC / boundary scan / Design-For-Testability |
| Paper # | DC2017-79 |
| Date of Issue | 2018-02-13 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2018/2/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC |
| Sub Title (in English) | |
| Keyword(1) | small delay fault |
| Keyword(2) | TSV |
| Keyword(3) | TDC |
| Keyword(4) | boundary scan |
| Keyword(5) | Design-For-Testability |
| 1st Author's Name | Satoshi Hirai |
| 1st Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2018-02-20 |
| Paper # | DC2017-79 |
| Volume (vol) | vol.117 |
| Number (no) | DC-444 |
| Page | pp.pp.13-18(DC), |
| #Pages | 6 |
| Date of Issue | 2018-02-13 (DC) |