| Presentation | 2018-02-20 Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to improve the yield and reliability of MRLD, in [6] we have developed the test approaches for detecting the interconnect faults including the stuck-at and bridge faults of MRLD. However, the test method for bridge faults of MRLD presented in [6] did not consider possible bridges between any interconnects in MRLD. Therefore, in this paper, we improve the test method of [6] for detecting the bridge faults between any interconnects that takes the Place-and-Route into account. The experimental results confirmed the effectiveness of the proposed test method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Device / MRLD / FPGA / Reliability / Interconnect defects / Testing |
| Paper # | DC2017-87 |
| Date of Issue | 2018-02-13 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2018/2/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Device |
| Keyword(2) | MRLD |
| Keyword(3) | FPGA |
| Keyword(4) | Reliability |
| Keyword(5) | Interconnect defects |
| Keyword(6) | Testing |
| 1st Author's Name | Senling Wang |
| 1st Author's Affiliation | Ehime University(Ehime Univ.) |
| 2nd Author's Name | Tatsuya Ogawa |
| 2nd Author's Affiliation | Ehime University(Ehime Univ.) |
| 3rd Author's Name | Yoshinobu Higami |
| 3rd Author's Affiliation | Ehime University(Ehime Univ.) |
| 4th Author's Name | Hiroshi Takahashi |
| 4th Author's Affiliation | Ehime University(Ehime Univ.) |
| 5th Author's Name | Masayuki Sato |
| 5th Author's Affiliation | TRL Corp.(TRL) |
| 6th Author's Name | Mitsunori Katsu |
| 6th Author's Affiliation | TRL Corp.(TRL) |
| 7th Author's Name | Shoichi Sekiguchi |
| 7th Author's Affiliation | TAIYOYUDEN(TAIYOYUDEN) |
| Date | 2018-02-20 |
| Paper # | DC2017-87 |
| Volume (vol) | vol.117 |
| Number (no) | DC-444 |
| Page | pp.pp.61-66(DC), |
| #Pages | 6 |
| Date of Issue | 2018-02-13 (DC) |