Presentation 2018-03-07
Minimizing End-to-end Latency in Circuit-switched Network for Parallel Computers
Yao Hu, Shoichi Hirasawa, Michihiro Koibuchi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Network congestion usually leads to increased communication time in supercomputer and datacenter networks. In our previous study, we have proposed an electrical circuit-switched (ECS) network to avoid network congestion and guarantee a certain amount of bandwidth for each communication pair, which makes its end-to-end latency predictable. In this report, we discuss several methods to minimize end-to-end latency in our ECS network. Through numerical analysis, we get upper and lower bounds of the end-to-end latency for one communication in the network and infer conditions of the minimum end-to-end latency. We thus come up with two methods to reach or approach the minimum latency: routing update and sending time slot adjustment. Furthermore, we design a hybrid CS/PS switch which takes both advantages of circuit switching and packet switching and also helps to reduce the minimum necessary number of slots for each switch in the network. Evaluation results show that our ECS network can obtain large benefits from complement of a small packet switching component.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) datacenter network / end-to-end latency / circuit switching / packet switching
Paper # CPSY2017-135,DC2017-91
Date of Issue 2018-02-28 (CPSY, DC)

Conference Information
Conference Date 2018/3/7(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinoshima Bunka-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) ETNET2018
Chair Koji Nakano(Hiroshima Univ.) / Michiko Inoue(NAIST) / Kiyoharu Hamaguchi(Shimane Univ.) / / Masahiro Goshima(NII)
Vice Chair Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Satoshi Fukumoto(Tokyo Metropolitan Univ.)
Secretary Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) / (Panasonic) / (Kochi Univ. of Tech.)
Assistant Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Masayuki Arai(Nihon Univ.)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Minimizing End-to-end Latency in Circuit-switched Network for Parallel Computers
Sub Title (in English)
Keyword(1) datacenter network
Keyword(2) end-to-end latency
Keyword(3) circuit switching
Keyword(4) packet switching
1st Author's Name Yao Hu
1st Author's Affiliation National Institute of Informatics(NII)
2nd Author's Name Shoichi Hirasawa
2nd Author's Affiliation National Institute of Informatics(NII)
3rd Author's Name Michihiro Koibuchi
3rd Author's Affiliation National Institute of Informatics(NII)
Date 2018-03-07
Paper # CPSY2017-135,DC2017-91
Volume (vol) vol.117
Number (no) CPSY-479,DC-480
Page pp.pp.95-100(CPSY), pp.95-100(DC),
#Pages 6
Date of Issue 2018-02-28 (CPSY, DC)