| Presentation | 2018-02-20 A test generation method based on k-cycle testing for finite state machines Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficient test generation methods are required. Since the test generation using the time expansion model focuses only on the circuit structure, it is difficult to achieve high fault coverage. In this paper, we propose Time Expansion Model with Initial State constraints (TEMIS) for the controller circuits and its test generation method. Experimental results show that our proposed method achieves 100% of fault coverage for a lot of controller circuits and they could gain higher fault coverage than TetraMax test generation using a time expansion model. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sequential test generation / finite state machines / k-cycle testing / register transfer level / controllers |
| Paper # | DC2017-81 |
| Date of Issue | 2018-02-13 (DC) |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2018/2/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A test generation method based on k-cycle testing for finite state machines |
| Sub Title (in English) | |
| Keyword(1) | sequential test generation |
| Keyword(2) | finite state machines |
| Keyword(3) | k-cycle testing |
| Keyword(4) | register transfer level |
| Keyword(5) | controllers |
| 1st Author's Name | Yuya Kinoshita |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Hideo Fujiwara |
| 3rd Author's Affiliation | Osaka Gakuin University(Osaka Gakuin Univ.) |
| Date | 2018-02-20 |
| Paper # | DC2017-81 |
| Volume (vol) | vol.117 |
| Number (no) | DC-444 |
| Page | pp.pp.25-30(DC), |
| #Pages | 6 |
| Date of Issue | 2018-02-13 (DC) |