| Presentation | 2018-02-20 A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability methods at register transfer level are important to enhance the efficiency of dynamic test compaction. In this paper, we propose a test register assignment method for concurrent operational unit testing to reduce the number of test patterns for transition faults on at-speed scan testing, and use controller augmentation as our design-for-testability method to enable the concurrent testing. It is expected that the efficiency of dynamic test compaction becomes high since concurrent operational unit testing can be executed for circuits which controller augmentation is applied. Experimental results for high-level benchmark circuits show that the number of test patterns was reduced by 7.35% with 0.45% rea overhead on average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test register assignment / controller augmentation / invaild test states / test scheduling |
| Paper # | DC2017-78 |
| Date of Issue | 2018-02-13 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2018/2/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation |
| Sub Title (in English) | |
| Keyword(1) | test register assignment |
| Keyword(2) | controller augmentation |
| Keyword(3) | invaild test states |
| Keyword(4) | test scheduling |
| 1st Author's Name | Yuki Takeuchi |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Shun Takeda |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Toshinori Hosokawa |
| 3rd Author's Affiliation | Nihon University(Nihon Univ.) |
| 4th Author's Name | Hiroshi Yamazaki |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Masayoshi Yoshimura |
| 5th Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| Date | 2018-02-20 |
| Paper # | DC2017-78 |
| Volume (vol) | vol.117 |
| Number (no) | DC-444 |
| Page | pp.pp.7-12(DC), |
| #Pages | 6 |
| Date of Issue | 2018-02-13 (DC) |