Presentation 2018-01-31
Investigation on Low-Energy Ferromagnetic Matrix Memory Using Adiabatic Quantum Flux Parametrons
Hayato Iwashita, Soya Taniguchi, Haruki Kato, Kyosuke Sano, Masamitsu Tanaka, Akira Fujimaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We study on matrix memory using patterned ferromagnetic materials for storage elements toward highly energy-efficient computing. The ferromagnetic pattern at the intersection point of selected bit line and word line is magnetized, and the direction of magnetization corresponds to 1-bit binary information. A 3-input AND gate based on the adiabatic quantum flux parametron is used for readout, by which ultra-low energy operation is expected. We confirmed correct operation of the proposed memory cell from numerical simulation of the equivalent circuit simulating the effect of residual magnetism. We have fabricated memory cells of read-only memory using Pd0.89Ni0.11 ferromagnetic patterns in order to experimentally verify the readout operation in matrix memory.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Ferromagnetic material / superconductor phase engineering / energy-efficient logic circuit
Paper # SCE2017-41
Date of Issue 2018-01-24 (SCE)

Conference Information
Committee SCE
Conference Date 2018/1/31(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) SQUID, high frequency, sensing technologies and their applications, etc.
Chair Hiroaki Myoren(Saitama Univ.)
Vice Chair
Secretary (National Defense Academy)
Assistant Hiroyuki Akaike(Daido Univ.)

Paper Information
Registration To Technical Committee on Superconductive Electronics
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Investigation on Low-Energy Ferromagnetic Matrix Memory Using Adiabatic Quantum Flux Parametrons
Sub Title (in English)
Keyword(1) Ferromagnetic material
Keyword(2) superconductor phase engineering
Keyword(3) energy-efficient logic circuit
1st Author's Name Hayato Iwashita
1st Author's Affiliation Nagoya University(Nagoya Univ.)
2nd Author's Name Soya Taniguchi
2nd Author's Affiliation Nagoya University(Nagoya Univ.)
3rd Author's Name Haruki Kato
3rd Author's Affiliation Nagoya University(Nagoya Univ.)
4th Author's Name Kyosuke Sano
4th Author's Affiliation Nagoya University(Nagoya Univ.)
5th Author's Name Masamitsu Tanaka
5th Author's Affiliation Nagoya University(Nagoya Univ.)
6th Author's Name Akira Fujimaki
6th Author's Affiliation Nagoya University(Nagoya Univ.)
Date 2018-01-31
Paper # SCE2017-41
Volume (vol) vol.117
Number (no) SCE-428
Page pp.pp.57-62(SCE),
#Pages 6
Date of Issue 2018-01-24 (SCE)