| Presentation | 2018-01-19 FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Field Programmable Gate Array (FPGA) is one of the promising medium for embedded systems. For CNN implementation on FPGA, it is required to consider the resource utilization of multiply-add circuit and memory access for weight of neural network. In this paper, we propose power of 2 approximation of weight. This method enables multiply-add circuit with Shifter and Adder. Our proposed method improved LUT consumption up to 2.5 times. Furthermore, the bit width required for weight was reduced to 5 bits in Convolutional layer and to 3bits in Fully connected layer. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Deep Learning / CNN |
| Paper # | VLD2017-82,CPSY2017-126,RECONF2017-70 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-ARC / VLD / CPSY / RECONF / IPSJ-SLDM |
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| Conference Date | 2018/1/18(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Masahiro Goshima(NII) / Hiroyuki Ochi(Ritsumeikan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Kiyoharu Hamaguchi(Shimane Univ.) |
| Vice Chair | / Noriyuki Minegishi(Mitsubishi Electric) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | (Kyushu Univ.) / Noriyuki Minegishi(Univ. of Tokyo) / Hidetsugu Irie(Toshiba) / Takashi Miyoshi(Nagoya Univ.) / Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(NTT) / (Utsunomiya Univ.) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Special Interest Group on System Architecture / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Deep Learning |
| Keyword(3) | CNN |
| 1st Author's Name | Takahiro Utsunomiya |
| 1st Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 2nd Author's Name | Motoki Amagasaki |
| 2nd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 3rd Author's Name | Masahiro Iida |
| 3rd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| Date | 2018-01-19 |
| Paper # | VLD2017-82,CPSY2017-126,RECONF2017-70 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-377,CPSY-378,RECONF-379 |
| Page | pp.pp.119-124(VLD), pp.119-124(CPSY), pp.119-124(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |