| Presentation | 2018-01-18 An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | VLD2017-64,CPSY2017-108,RECONF2017-52 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-ARC / VLD / CPSY / RECONF / IPSJ-SLDM |
|---|---|
| Conference Date | 2018/1/18(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Masahiro Goshima(NII) / Hiroyuki Ochi(Ritsumeikan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Kiyoharu Hamaguchi(Shimane Univ.) |
| Vice Chair | / Noriyuki Minegishi(Mitsubishi Electric) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | (Kyushu Univ.) / Noriyuki Minegishi(Univ. of Tokyo) / Hidetsugu Irie(Toshiba) / Takashi Miyoshi(Nagoya Univ.) / Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(NTT) / (Utsunomiya Univ.) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Special Interest Group on System Architecture / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL |
| Sub Title (in English) | |
| Keyword(1) | |
| 1st Author's Name | Takumu Uyama |
| 1st Author's Affiliation | Tokyo Institute of Technology(Titech) |
| 2nd Author's Name | Tomoya Fujii |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Titech) |
| 3rd Author's Name | Haruyoshi Yonekawa |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Titech) |
| 4th Author's Name | Shimpei Sato |
| 4th Author's Affiliation | Tokyo Institute of Technology(Titech) |
| 5th Author's Name | Hiroki Nakahara |
| 5th Author's Affiliation | Tokyo Institute of Technology(Titech) |
| Date | 2018-01-18 |
| Paper # | VLD2017-64,CPSY2017-108,RECONF2017-52 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-377,CPSY-378,RECONF-379 |
| Page | pp.pp.13-18(VLD), pp.13-18(CPSY), pp.13-18(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |