| Presentation | 2018-01-27 A study on FPGA implementation of SAM spiking neural network Minoru Motoki, Kazunori Matsuo, Hirohito Shintani, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | his paper describes a design for FPGA implementation of SAM spiking neural network and experimental results of circuit resource and non-linear function approximation performances. We have already proposed a supervised training algorithm for the SAM neuron model. The algorithm has a characteristic which allows multiplierless structure, therefore, the implementation of the SAM neural network into FPGAs can be achieved as ``on-chip learning''. We confirmed that the model was able to be multiplierless structure by the logic synthesis using Quartus Prime Lite. Moreover, we inspected that circuit scales and performances of the task of 3rd degree polynomial function approximation when varying the number of the hidden neurons. As the result, it was clarified that the number of the logic elements which proportions to the number of the hidden neurons was required. In addition, the SAM network achieved a performance that RMS error was less than 0.025 when the network structure was 5:30:5. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | spiking neural network / SAM neuron model / supervised learning / FPGA / on-chip learning / function approximation |
| Paper # | NC2017-65 |
| Date of Issue | 2018-01-19 (NC) |
| Conference Information | |
| Committee | MBE / NC / NLP |
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| Conference Date | 2018/1/26(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyushu Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ME, generalImplementation of Neuro Computing,Analysis and Modeling of Human Science, |
| Chair | Kazuki Nakajima(Univ. of Toyama) / Masafumi Hagiwara(Keio Univ.) / Masaharu Adachi(Tokyo Denki Univ.) |
| Vice Chair | Masaki Kyoso(TCU) / Yutaka Hirata(Chubu Univ.) / Norikazu Takahashi(Okayama Univ.) |
| Secretary | Masaki Kyoso(Toyama Pref. Univ.) / Yutaka Hirata(Kindai Univ.) / Norikazu Takahashi(Tokyo Inst. of Tech.) |
| Assistant | Kim Juhyon(Univ. of Toyama) / Takumi Kobayashi(YNU) / Yoshihisa Shinozawa(Keio Univ.) / Keiichiro Inagaki(Chubu Univ.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Masayuki Kimura(Kyoto Univ.) |
| Paper Information | |
| Registration To | Technical Committee on ME and Bio Cybernetics / Technical Committee on Neurocomputing / Technical Committee on Nonlinear Problems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study on FPGA implementation of SAM spiking neural network |
| Sub Title (in English) | |
| Keyword(1) | spiking neural network |
| Keyword(2) | SAM neuron model |
| Keyword(3) | supervised learning |
| Keyword(4) | FPGA |
| Keyword(5) | on-chip learning |
| Keyword(6) | function approximation |
| 1st Author's Name | Minoru Motoki |
| 1st Author's Affiliation | National Institute of Technology, Kumamoto College(NIT, Kumamoto Col.) |
| 2nd Author's Name | Kazunori Matsuo |
| 2nd Author's Affiliation | National Institute of Technology, Kumamoto College(NIT, Kumamoto Col.) |
| 3rd Author's Name | Hirohito Shintani |
| 3rd Author's Affiliation | National Institute of Technology, Kumamoto College(NIT, Kumamoto Col.) |
| Date | 2018-01-27 |
| Paper # | NC2017-65 |
| Volume (vol) | vol.117 |
| Number (no) | NC-417 |
| Page | pp.pp.89-94(NC), |
| #Pages | 6 |
| Date of Issue | 2018-01-19 (NC) |