| Presentation | 2018-01-19 Mutant Generation of Performance Tests for LLVM Back-Ends Kenji Tanaka, Nagisa Ishiura, Masanari Nishimura, Akiya Fukui, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This article presents a method of testing optimization capability of LLVM back-ends by generating functionally equivalent test mutants from existing test programs. Since the LLVM back-ends perform various target dependent and peephole optimization as well as transformations for code generation, it is necessary to test if optimization is properly done as designed to enhance performance, not to mention if generated codes are correct. Test programs for the performance test are usually developed manually by compiler designers, which do not always provide enough variation to cover corner cases. The method in this article attempts to augment test cases by generating mutants from existing test programs. The mutation in our method is designed not to change the functionality of the original test programs, so that insufficient optimization is detected by mechanical comparison of assembly codes. In a preliminary experiment on the LLVM 6.0.0 back-end for x86_64, a tool based on the proposed method has found two interesting cases which might contribute toward performance improvement of the back-end. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | LLVM IR / Back-Ends / Mutation / Optimization |
| Paper # | VLD2017-88,CPSY2017-132,RECONF2017-76 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-ARC / VLD / CPSY / RECONF / IPSJ-SLDM |
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| Conference Date | 2018/1/18(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Masahiro Goshima(NII) / Hiroyuki Ochi(Ritsumeikan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Kiyoharu Hamaguchi(Shimane Univ.) |
| Vice Chair | / Noriyuki Minegishi(Mitsubishi Electric) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | (Kyushu Univ.) / Noriyuki Minegishi(Univ. of Tokyo) / Hidetsugu Irie(Toshiba) / Takashi Miyoshi(Nagoya Univ.) / Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(NTT) / (Utsunomiya Univ.) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Special Interest Group on System Architecture / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Mutant Generation of Performance Tests for LLVM Back-Ends |
| Sub Title (in English) | |
| Keyword(1) | LLVM IR |
| Keyword(2) | Back-Ends |
| Keyword(3) | Mutation |
| Keyword(4) | Optimization |
| 1st Author's Name | Kenji Tanaka |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 3rd Author's Name | Masanari Nishimura |
| 3rd Author's Affiliation | Renesas Electronics Corporation(Renesas) |
| 4th Author's Name | Akiya Fukui |
| 4th Author's Affiliation | Renesas Electronics Corporation(Renesas) |
| Date | 2018-01-19 |
| Paper # | VLD2017-88,CPSY2017-132,RECONF2017-76 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-377,CPSY-378,RECONF-379 |
| Page | pp.pp.169-174(VLD), pp.169-174(CPSY), pp.169-174(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |