| Presentation | 2017-12-14 STRAIGHTアーキテクチャの命令形式を利用したスケジューラの提案 Seiya Akaki, Hidetsugu Irie, Shuichi Sakai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The single thread performance of a processor supports the entire system capability by reducing the critical path latency of the program.STRAIGHT has been developed as a processor architecture to improve single thread performance.STRAIGHT has a unique instruction format of specyfying source operands by instruction distance. This removes register renaming and makes it possible to construct an efficient Out-of-Order execution mechanism.This paper proposes the configuration of the scheduling logic using the instruction format of STRAIGHT. The proposed STRAIGHT scheduler simplify its hardware by using the fact that the operand is expressed as instruction distance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | microarchitecture / CPU / scheduler / hardware |
| Paper # | CAS2017-71,ICD2017-59,CPSY2017-68 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY / CAS |
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| Conference Date | 2017/12/14(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Art Hotel Ishigakijima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Mitsuru Hiraki(Renesas) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hideaki Okazaki(Shonan Inst. of Tech.) |
| Secretary | Makoto Nagata(Univ. of Tokyo) / Hidetsugu Irie(Panasonic) / Takashi Miyoshi(Utsunomiya Univ.) / Hideaki Okazaki(Hokkaido Univ.) |
| Assistant | Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yohei Nakamura(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems / Technical Committee on Circuits and Systems |
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| Language | JPN-ONLY |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | microarchitecture |
| Keyword(2) | CPU |
| Keyword(3) | scheduler |
| Keyword(4) | hardware |
| 1st Author's Name | Seiya Akaki |
| 1st Author's Affiliation | The University of Tokyo(UT) |
| 2nd Author's Name | Hidetsugu Irie |
| 2nd Author's Affiliation | The University of Tokyo(UT) |
| 3rd Author's Name | Shuichi Sakai |
| 3rd Author's Affiliation | The University of Tokyo(UT) |
| Date | 2017-12-14 |
| Paper # | CAS2017-71,ICD2017-59,CPSY2017-68 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-343,ICD-344,CPSY-345 |
| Page | pp.pp.43-44(CAS), pp.43-44(ICD), pp.43-44(CPSY), |
| #Pages | 2 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |