| Presentation | 2017-12-14 A proposal for Improving Security of Adiabatic Reversible Logic Based on PADDL Tomotaka Nishiwaki, Yasuhiro Takahashi, Toshikazu Sekine, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An adiabatic logic is one of the low power consumption performance improvement by circuit technology for integrated circuit.PADDL is an adiabatic reversible logic in which all basic two-input logic circuits can be executed.Previously, we proposed an adiabatic reversible logic which has the same function with fewer transistors than PADDL.However, there was a problem that the peak variation in the power waveform was inferior and the security was deteriorated.In this paper, we propose a new adiabatic reversible logic that maintains the characteristics of PADDL, and aims to further reduce the energy consumption and improve the power variation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | adiabatic logic / reversible logic / secure |
| Paper # | CAS2017-88,ICD2017-76,CPSY2017-85 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY / CAS |
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| Conference Date | 2017/12/14(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Art Hotel Ishigakijima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Mitsuru Hiraki(Renesas) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hideaki Okazaki(Shonan Inst. of Tech.) |
| Secretary | Makoto Nagata(Univ. of Tokyo) / Hidetsugu Irie(Panasonic) / Takashi Miyoshi(Utsunomiya Univ.) / Hideaki Okazaki(Hokkaido Univ.) |
| Assistant | Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yohei Nakamura(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems / Technical Committee on Circuits and Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A proposal for Improving Security of Adiabatic Reversible Logic Based on PADDL |
| Sub Title (in English) | |
| Keyword(1) | adiabatic logic |
| Keyword(2) | reversible logic |
| Keyword(3) | secure |
| 1st Author's Name | Tomotaka Nishiwaki |
| 1st Author's Affiliation | Gifu University(Gifu Univ.) |
| 2nd Author's Name | Yasuhiro Takahashi |
| 2nd Author's Affiliation | Gifu University(Gifu Univ.) |
| 3rd Author's Name | Toshikazu Sekine |
| 3rd Author's Affiliation | Gifu University(Gifu Univ.) |
| Date | 2017-12-14 |
| Paper # | CAS2017-88,ICD2017-76,CPSY2017-85 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-343,ICD-344,CPSY-345 |
| Page | pp.pp.113-117(CAS), pp.113-117(ICD), pp.113-117(CPSY), |
| #Pages | 5 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |