| Presentation | 2017-12-15 A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs Yousuke Miyake, Yasuo Sato, Seiji Kajihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliability by self-testing in FPGAs. Although an external observation with an oscilloscope has been used for evaluation of the variable test clock, there are some problems with the external observation, such as errors of the oscilloscope itself or measurement instruments. Furthermore, it is impractical to guarantee accuracy of the variable test clock based on the external observation for all fabricated chips. In order to guarantee the accuracy, it is necessary to observe the generated clock in the chip. This paper proposes a test clock observation method using a TDC (Time-to-Digital Converter) circuit that can be implemented on FPGAs, and then evaluates its effectiveness using Altera Cyclone IV FPGA. This paper also discusses an accuracy evaluation of the variable test clock for delay measurement in FPGAs by using the proposed observation method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Built-In Self-Test / Delay testing / Variable test clock / Time-to-Digital Converter |
| Paper # | DC2017-75 |
| Date of Issue | 2017-12-08 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2017/12/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Akita Study Center, The Open University of Japan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Winter Workshop on safety |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Built-In Self-Test |
| Keyword(3) | Delay testing |
| Keyword(4) | Variable test clock |
| Keyword(5) | Time-to-Digital Converter |
| 1st Author's Name | Yousuke Miyake |
| 1st Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 2nd Author's Name | Yasuo Sato |
| 2nd Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 3rd Author's Name | Seiji Kajihara |
| 3rd Author's Affiliation | Kyushu Institute of Technology(KIT) |
| Date | 2017-12-15 |
| Paper # | DC2017-75 |
| Volume (vol) | vol.117 |
| Number (no) | DC-359 |
| Page | pp.pp.37-42(DC), |
| #Pages | 6 |
| Date of Issue | 2017-12-08 (DC) |