| Presentation | 2017-12-14 Design of Quick-Lock Reference-Clock-Less All-Digital CDR using Delay Tunable Buffer for Lock Range Extension Meikan Chin, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A quick-lock reference-clock-less all-digital burst-mode CDR is proposed. Since the proposed CDR resumes from a standby state soon after a 4-bit preamble and consumes no dynamic power in its standby state, it will improve the total power efficiency of serial communications which work intermittently such as mobile and sensor networks. A phase-selection technique using delay tunable buffer and Vernier TDC is introduced for lock range extension and low power consumption. A prototype implemented in 65nm CMOS technology works at 1.0--2.5 Gbps and consumes 5.6--8.8 mW from the 1.0V supply in simulations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Clock Data Recovery / Burst-Mode CDR / Reference-Clock-Less / All-Digital |
| Paper # | CAS2017-64,ICD2017-52,CPSY2017-61 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY / CAS |
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| Conference Date | 2017/12/14(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Art Hotel Ishigakijima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Mitsuru Hiraki(Renesas) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hideaki Okazaki(Shonan Inst. of Tech.) |
| Secretary | Makoto Nagata(Univ. of Tokyo) / Hidetsugu Irie(Panasonic) / Takashi Miyoshi(Utsunomiya Univ.) / Hideaki Okazaki(Hokkaido Univ.) |
| Assistant | Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yohei Nakamura(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems / Technical Committee on Circuits and Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Quick-Lock Reference-Clock-Less All-Digital CDR using Delay Tunable Buffer for Lock Range Extension |
| Sub Title (in English) | |
| Keyword(1) | Clock Data Recovery |
| Keyword(2) | Burst-Mode CDR |
| Keyword(3) | Reference-Clock-Less |
| Keyword(4) | All-Digital |
| Keyword(5) | |
| 1st Author's Name | Meikan Chin |
| 1st Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| 2nd Author's Name | Tetsuya Iizuka |
| 2nd Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| 3rd Author's Name | Toru Nakura |
| 3rd Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| 4th Author's Name | Kunihiro Asada |
| 4th Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| Date | 2017-12-14 |
| Paper # | CAS2017-64,ICD2017-52,CPSY2017-61 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-343,ICD-344,CPSY-345 |
| Page | pp.pp.3-8(CAS), pp.3-8(ICD), pp.3-8(CPSY), |
| #Pages | 6 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |