| Presentation | 2017-12-14 Study on acceleration of Paralleled Linear Feedback Shift Register PRBS Generator Keisuke Iyama, Masaki Ishii, Masahiro Sasaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The operation speed of the on-chip test pattern generator that tests normal operation of LSI chip is determined by the propagation delay of D-FF and EXOR used in the feedback section of the PRBS generator using linear feedback shift register (LFSR).When the clock frequency too fast, D-FF latches before EXOR output is determined, generated PRBS is incorrect.In this study, we propose a high speed LFSR by ignoring the delay of EXOR and delaying the latch timing of feedback D-FF.We confirm that 16 GHz PRBS can be generated by simulation, and show the effectiveness of the proposed circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PRBS / BIST / LFSR / serial interface |
| Paper # | CAS2017-85,ICD2017-73,CPSY2017-82 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY / CAS |
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| Conference Date | 2017/12/14(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Art Hotel Ishigakijima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Mitsuru Hiraki(Renesas) |
| Vice Chair | Makoto Nagata(Kobe Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hideaki Okazaki(Shonan Inst. of Tech.) |
| Secretary | Makoto Nagata(Univ. of Tokyo) / Hidetsugu Irie(Panasonic) / Takashi Miyoshi(Utsunomiya Univ.) / Hideaki Okazaki(Hokkaido Univ.) |
| Assistant | Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yohei Nakamura(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems / Technical Committee on Circuits and Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study on acceleration of Paralleled Linear Feedback Shift Register PRBS Generator |
| Sub Title (in English) | |
| Keyword(1) | PRBS |
| Keyword(2) | BIST |
| Keyword(3) | LFSR |
| Keyword(4) | serial interface |
| 1st Author's Name | Keisuke Iyama |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Masaki Ishii |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 3rd Author's Name | Masahiro Sasaki |
| 3rd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| Date | 2017-12-14 |
| Paper # | CAS2017-85,ICD2017-73,CPSY2017-82 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-343,ICD-344,CPSY-345 |
| Page | pp.pp.99-99(CAS), pp.99-99(ICD), pp.99-99(CPSY), |
| #Pages | 1 |
| Date of Issue | 2017-12-07 (CAS, ICD, CPSY) |